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Dive into the research topics where Chee-Yee Chung is active.

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Featured researches published by Chee-Yee Chung.


IEEE Transactions on Advanced Packaging | 2001

Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology

Alex Waizman; Chee-Yee Chung

Extended adaptive voltage positioning (EAVP) is a new robust methodology for the design and analysis of a low impedance resonant free power delivery network, which utilizes and extends the theory of adaptive voltage positioning (AVP) that is commonly used in voltage regulator module (VRM) design and operation. Using EAVP, uncertainties in design guardband noise budget can be removed, resulting in significant performance bin-split improvement and cost reduction. Design optimization of decoupling capacitors with EAVP will be illustrated by using both time and frequency domain analysis.


electronic components and technology conference | 2001

Low cost flip chip package design concepts for high density I/O

Tee-Onn Chong; Seng-Hooi Ong; Teong-Guan Yew; Chee-Yee Chung; Robert L. Sankman

The semiconductor industry at large is migrating from wire bond packaging to flip chip packaging due to electrical performance requirements. With the removal of the highly resistive and inductive wire bonds, high-speed buses achieve well-controlled characteristic impedance for signal wave propagation and lower impedance for the power delivery network. However, a disadvantage of flip chip packaging is its lower input/output (I/O) routing density when compared to wire bond packaging. To meet the high I/O count for certain products, innovative flip chip bump patterns and creative routing options are needed. This paper will outline some innovative package design concepts on both die to package, defined as level 1 interconnect, and package to motherboard (MB), defined as level 2 interconnect, to increase the I/O signal routing density without increasing the package or MB cost.


Archive | 2000

Embedded capacitor assembly in a package

David G. Figueroa; Yuan-Liang Li; Chee-Yee Chung


Archive | 2003

Dual referenced microstrip

James Breisch; Chee-Yee Chung; Alex Waizman; Teong Guan Yew


Archive | 2000

System and method for package socket with embedded power and ground planes

Chee-Yee Chung; David G. Figueroa; Kris Frutschy; Bob Sankman; Farzaneh Yahyaei-Moayyed


Archive | 2000

Embedded enclosure for effective electromagnetic radiation reduction

Yuan-Liang Li; Chee-Yee Chung; David G. Figueroa


Archive | 1999

Chip package and method

Alex Waizman; Chee-Yee Chung; Bob Sankman


Archive | 2001

Arrangements to supply power to semiconductor package

Kristopher Frutschy; Chee-Yee Chung; Bob Sankman


Archive | 2001

Integral capacitor with electromagnetic radiation reduction

Yuan-Liang Li; Chee-Yee Chung; David G. Figueroa


Archive | 2002

Method of fabrication for a socket with embedded conductive structure

David G. Figueroa; Chee-Yee Chung; Kristopher Frutschy; Farzaneh Yahyaei-Moayyed

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