David J. Widiger

Two-dimensional transient simulation of an idealized high electron mobility transistor

We develop a model for the high electron mobility transistor (HEMT) in which we include both hot-electron effects and conduction outside the quantum subband system using hydrodynamic-like transport equations. With such a model we can assess the significance of the various physical phenomena involved in the operation of the HEMT. We calculate results with a two-dimensional numerical technique for both steady-state and transient operation. For a 3-µm device at 77 K, we determine a transconductance of 450 mS/mm, a current-switching speed of 6 ps, and a capacitive charging speed of 4 ps/fanout gate which corresponds to the performance measured by other workers. We also see that electronic heating, velocity overshoot, and conduction outside the quantum well are significant near the pinchoff point. We conclude that the advantage of HEMT is twofold. The excellent conduction in the quantum well results in a low access resistance, and the low impurity concentration in the GaAs results in optimum overshoot effects.

Scaling properties of high electron mobility transistors

We present the scaling properties of an idealized HEMT structure at 300 K. A two-dimensional device model based on three moments of the Boltzmann equation is used to investigate a constant voltage scaling scheme. Detailed results are presented for gate lengths of 2.0, 1.33, 1.0, 0.67, and 0.50 µm.

The potential of complementary heterostructure FET IC's

The performance capability of AlGaAs/GaAs complementary heterostructure FET (C-HFET) integrated circuits has been evaluated in computer simulations. The study is focused on C-HFET designs in which static currents and gate-leakage currents are sufficiently low to take full advantage of the speed, power dissipation, and logic function capabilities of CMOS-like circuitry. ASTAP computer simulations for loaded NAND and NOR circuits are examined over a wide supply-voltage range at both 300 and 77 K in order to determine the potential of various MODFET, MISFET, and SISFET approaches as well as the prospects of future designs. While performance is limited by FET threshold and gate leakage in present C-HFET approaches, the speed of properly designed 0.7-µm C-HFETs at 300 K is projected to be 3 × faster than comparable 300 K Si-CMOS circuits. C-HFET circuits at 77 K are projected to be more than 4 × faster than 77 K Si-CMOS circuits. It is also found that properly designed C-HFETs could operate at speeds close to those of DCFL n-channel HFET circuits while dissipating only 1/10 of the power.

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.

Parallelized Full Package Signal Integrity Analysis Using Spatially Distributed 3D Circuit Models

Full package signal integrity analysis is parallelized in a suite of tools called PATS (package analysis tool suite). PATS extracts sparse circuit models using a segment-to-segment BEM (boundary element method) algorithm for both capacitance and inverse inductance and uses a fixed-time step circuit simulator to create time-domain scattering models. Critical issues regarding the parallelization of PATS and segment-to-segment BEM circuit models are explored. Examples demonstrating the accuracy of this approach are presented for real packaging cases

Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters

Recent CAD methodologies of design-for-manufacturability (DFM) have naturally led to a significant increase in the number of process and layout parameters that have to be taken into account in design-rule checking. Methodological consistency requires that a similar number of parameters be taken into account during layout parasitic extraction. Because of the inherent variability of these parameters, the issue of efficiently extracting deterministic parasitic sensitivities with respect to such a large number of parameters must be addressed. In this paper, we tackle this very issue in the context of capacitance sensitivity extraction. In particular, we show how the adjoint sensitivity method can be efficiently integrated within a finite-difference (FD) scheme to compute the sensitivity of the capacitance with respect to a large set of BEOL parameters. If np is the number of parameters, the speedup of the adjoint method is shown to be a factor of np/2 with respect to direct FD sensitivity techniques. The proposed method has been implemented and verified on a 65 nm BEOL cross section having 10 metal layers and a total number of 59 parameters. Because of its speed, the method can be advantageously used to prune out of the CAD flow those BEOL parameters that yield a capacitance sensitivity less than a given threshold.

R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip

A coupling noise evaluation of a high performance S/390 microprocessor using a full chip RLC extraction and simulation process is presented. Review of on-chip wiring guidelines with respect to the inaccuracies of an RC coupling evaluation for known net topologies is discussed in terms of tool requirements for full-chip noise evaluation which include inductive coupling effects. The extraction and simulation approach is described in terms of algorithms and procedures used to account for the frequency dependent RLC effects in a manner that allow a full chip noise evaluation. Results are presented which compare noise amplitude differences between RC and R(f)L(f)C evaluations for the wiring data of an S/390 microprocessor as well as pertinent statistics such as run times and memory usage.

Understanding common-mode noise on wide data-buses

This paper discusses the effects of the frequency-dependent losses in the reference return path for wide, on-chip data buses, that must be understood in order to accurately predict the interaction and summation of crosstalk and common-mode noise signals. This interaction can generate excessive noise for on-chip global interconnections. Measured and simulated results are shown for representative 8-12 line couplings and circuit-synthesis techniques are shown to capture the correct R(f)L(f)C behavior of the reference series impedance.

Variable frequency crosstalk noise analysis: a methodology to guarantee functionality from dc to f/sub max/

One means of reducing pessimism in crosstalk analysis is to consider timing orthogonality. While earlier works have addressed the temporal alignment of timing windows [1, 2, 3, 4], these treatments have overlooked one key point. Crosstalk noise failures are frequency dependent. A chip that functions at one frequency can fail due to crosstalk noise at faster and slower frequencies. Moreover, because system developers and manufacturers need chips that operate over a wide range of frequencies, noise analysis tools should guarantee a wide range of operation. In this paper, we explain this phenomenon and propose a simple procedure to include timing information and guarantee functionality from dc to fmax.

Frequency dependent RLC crosstalk evaluation of a high performance S/390 microprocessor chip

A coupling noise evaluation of a high performance S/390 microprocessor using a full chip RLC extraction and simulation process is presented. Review of on-chip wiring guidelines with respect to the inaccuracies of an RC coupling evaluation for known net topologies is discussed in terms of tool requirements for full-chip noise evaluation which include inductive coupling effects. The extraction and simulation approach is described in terms of algorithms and procedures used to account for the frequency dependent RLC effects in a manner that allow a full chip noise evaluation. Results are presented which compare noise amplitude differences between RC and R(f)L(f)C evaluations for the wiring data of a S/390 microprocessor as well as pertinent statistics such as run times and memory usage.