Gerard V. Kopcsay

Overview of the Blue Gene/L system architecture

The Blue Gene®/L computer is a massively parallel supercomputer based on IBM system-on-a-chip technology. It is designed to scale to 65,536 dual-processor nodes, with a peak performance of 360 teraflops. This paper describes the project objectives and provides an overview of the system architecture that resulted. We discuss our application-based approach and rationale for a low-power, highly integrated design. The key architectural features of Blue Gene/L are introduced in this paper: the link chip component and five Blue Gene/L networks, the PowerPC® 440 core and floating-point enhancements, the on-chip and off-chip distributed memory system, the node- and system-level design for high reliability, and the comprehensive approach to fault isolation.

On-chip wiring design challenges for gigahertz operation

This paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates.

High-speed signal propagation on lossy transmission lines

This paper addresses some of the problems encountered in propagating high-speed signals on lossy transmission lines encountered in high-performance computers. A technique is described for including frequency-dependent losses, such as skin effect and dielectric dispersion, in transmission line analyses. The disjoint group of available tools is brought together, and their relevance to the propagation of high-speed pulses in digital circuit applications is explained. Guidelines are given for different interconnection technologies to indicate where the onset of severe dispersion takes place. Experimental structures have been built and tested, and this paper reports on their electrical performance and demonstrates the agreement between measured data and waveforms derived from analysis. The paper addresses the problems found on lossy lines, such as reflections, rise-time slowdown, increased delay, attenuation, and crosstalk, and suggests methods for controlling these effects in order to maintain distortion-free propagation of high-speed signals.

When are transmission-line effects important for on-chip interconnections

Short, medium and long on-chip interconnections having line widths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Characterization of resistive transmission lines by short-pulse propagation

A method for completely characterizing resistive transmission lines by short-pulse propagation is described. Using the loss and dispersion of pulses propagated on two different lengths of line, together with the measured low-frequency capacitance, the frequency-dependent propagation constant, attenuation, and the complex impedance are determined. The basic method is demonstrated with results from low-loss cables and a well-controlled coplanar waveguide sample.<<ETX>>

Extraction of /spl epsiv//sub r/(f) and tan/spl delta/(f) for printed circuit board insulators up to 30 GHz using the short-pulse propagation technique

In this paper, the self-consistent, frequency-dependent dielectric constant epsivr(f) and dielectric loss tandelta(f) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-domain excitations and provides validation of the measurement and model generation technique

Frequency-dependent losses on high-performance interconnections

This paper compares the major classes of chip-to-chip and on-chips interconnections used in high-performance computers and communication systems and reviews their electrical characteristics. Measurement results of dielectric loss are shown and the attenuation is compared for printed-circuit-board, glass-ceramic, thin-film, and on-chip wiring. Simulation results are shown with representative driver and receiver circuits, guidelines are given for when losses are significant, and predictions are made for the sustainable bandwidths on useful wiring lengths.

Blue Gene/L advanced diagnostics environment

This paper describes the Blue Gene®/L advanced diagnostics environment (ADE) used throughout all aspects of the Blue Gene/L project, including design, logic verification, bring-up, diagnostics, and manufacturing test. The Blue Gene/L ADE consists of a lightweight multithreaded coherence-managed kernel, runtime libraries, device drivers, system programming interfaces, compilers, and host-based development tools. It provides complete and flexible access to all features of the Blue Gene/L hardware. Prior to the existence of hardware, ADE was used on Very high-speed integrated circuit Hardware Description Language (VHDL) models, not only for logic verification, but also for performance measurements, code-path analysis, and evaluation of architectural tradeoffs. During early hardware bring-up, the ability to run in a cycle-reproducible manner on both hardware and VHDL proved invaluable in fault isolation and analysis. However, ADE is also capable of supporting high-performance applications and parallel test cases, thereby permitting us to stress the hardware to the limits of its capabilities. This paper also provides insights into system-level and device-level programming of Blue Gene/L to assist developers of high-performance applications o more fully exploit the performance of the machine.

Packaging the Blue Gene/L supercomputer

As 1999 ended, IBM announced its intention to construct a one-petaflop supercomputer. The construction of this system was based on a cellular architecture--the use of relatively small but powerful building blocks used together in sufficient quantities to construct large systems. The first step on the road to a petaflop machine (one quadrillion floating-point operations in a second) is the Blue Gene®/L supercomputer. Blue Gene/L combines a low-power processor with a highly parallel architecture to achieve unparalleled computing performance per unit volume. Implementing the Blue Gene/L packaging involved trading off considerations of cost, power, cooling, signaling, electromagnetic radiation, mechanics, component selection, cabling, reliability, service strategy, risk, and schedule. This paper describes how 1,024 dual-processor compute application-specific integrated circuits (ASICs) are packaged in a scalable rack, and how racks are combined and augmented with host computers and remote storage. The Blue Gene/L interconnect, power, cooling, and control systems are described individually and as part of the synergistic whole.

The importance of inductance and inductive coupling for on-chip wiring

The importance of inductance and inductive coupling for accurate delay and crosstalk prediction in on-chip interconnections is investigated experimentally for the top three layers in a five-layer wiring structure and guidelines are formulated. In-plane and between-plane crosstalk and delay dependence on driver and receiver circuit device sizes and line lengths and width are analyzed with representative CMOS circuits. Simplified constant-parameter, distributed coupled-line RLC-circuit representation that approximates the waveforms predicted with frequency-dependent line parameters is shown to be feasible.