Byron Krauter

On-chip wiring design challenges for gigahertz operation

This paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates.

Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis

It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines. Furthermore, it is also understood that these circuits can be synthesized knowing only the high and the low frequency resistances and inductances. Existing VLSI extraction tools however, are not efficient enough to solve for the frequency dependent resistances and inductances on large VLSI layouts, nor do they synthesize circuits suitable for timing analysis. We propose a rules-based method that efficiently and accurately captures the high and low frequency characteristics directly from layout shapes, and subsequently synthesizes a simple frequency independent ladder circuit suitable for timing analysis. We compare our results to other simulation results.

The circuit and physical design of the POWER4 microprocessor

The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

Generating sparse partial inductance matrices with guaranteed stability

This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding the smallest matrix terms, the proposed approach maintains accuracy at middle and high frequencies and is guaranteed to be positive definite for any degree of sparsity (thereby producing stable circuit solutions). While the proposed technique is strictly based upon potential theory (i.e. the invariance of potential differences on the zero potential reference choice), the technique is, nevertheless, presented and discussed in both circuit and magnetic terms. The conventional and the proposed sparse formulation techniques are contrasted in terms of eigenvalues and circuit simulation results on practical examples.

The Elmore Delay as a Bound for RC Trees with Generalized Input Signals

The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation. In this paper, we prove that the Elmore delay is an absolute upper bound on the 50% delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation.

The clock distribution of the POWER4 microprocessor

The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.

Including inductive effects in interconnect timing analysis

Including inductive effects in interconnect timing analysis has become increasingly important in todays deep submicron designs. In this tutorial paper we will describe the technology trends that brought us to this juncture, summarize when inductance should be included, and consider some of the extraction and modeling techniques available. This coverage will not be an exhaustive summary of all the extraction and analysis techniques available, but one that is primarily focused on extraction methods that efficiently capture frequency dependence due to proximity effects and moment-based analysis techniques.

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

This paper illustrates the growing significance of self and mutual inductances by examining their effects on performance and characteristic issues like propagation delay, rise time, and overshoots. This paper introduces Elmore-like closed form solutions to analyze the behavior of integrated circuits in the presence of self and mutual inductances. The complexity of the expressions introduced here is linear with the number of elements in the interconnect network, and has Elmore delay accuracy characteristics. The propagation delay and overshoots estimated based on these formulae are within 15% of AS/X simulations for a wide range of interconnects from IBMs most recent CMOS technology.

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses

Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of the magnetic couplings for final design verification can be a daunting task. In general, when modeling inductance and the associated return paths, one must consider the on-chip conductors as well as the system packaging. This can result in an RLC circuit size that is impractical for traditional simulators. In this paper we demonstrate a localized, window-based extraction and simulation methodology that employs the recently proposed susceptance (the inverse of inductance matrix) concept. We provide a qualitative explanation for the efficacy of this approach, and demonstrate how it facilitates pre-manufacturing simulations that would otherwise be intractable. A critical aspect of this simulation efficiency is owed to a susceptance-based circuit formation that we prove to be symmetric positive definite. This property, along with the sparsity of the susceptance matrix, enables the use of some advanced sparse matrix solvers. lye demonstrate this extraction and simulation methodology on some industrial examples.

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.