David James Mcculloch

Novel fingerprint scanning arrays using polysilicon TFT's on glass and polymer substrates

Novel fingerprint scanning arrays based upon capacitance sensing have been made. Each sensor element consists of a capacitor electrode and two poly-Si thin film transistors for addressing and read out. The devices were fabricated on glass, polyimide and polyethersulphone substrates using a low temperature (<250/spl deg/C) process.

Excimer-laser-annealed poly-Si thin-film transistors

The crystallization of alpha -Si:H into poly-Si using an excimer laser has been examined. The resulting microstructure was found to be stratified into a large-grain surface region, formed from the liquid phase, and a fine-grain underlying layer, thought to be formed by solid phase crystallization. The threshold beam energies for these sequential phase changes were identified from surface reflectance measurements after crystallization and the energies increased with diminishing hydrogen content of the material. The electrical characteristics of thin-film transistors made with material crystallized at energies close to the melt threshold could be correlated with the limited depth of large-grain material. For significantly higher beam energies, coplanar structures showed a severe degradation in leakage current due to lateral diffusion of phosphorus, across the channel from the source and drain regions. When this effect was avoided, thin-film transistors with field-effect mobilities up to 160 cm/sup 2//V-s and on/off current ratios up to 10/sup 8/ were obtained. >

Influence of melt depth in laser crystallized poly-Si thin film transistors

The influence of film thickness and incident excimer laser energy density on the properties of poly-Si thin film transistors has been investigated and a coherent pattern of behavior has been identified which establishes controlled melt-through of the film as a key condition for achieving high quality devices. The conditions were correlated with the appearance of large grains and gave consistent results from both n- and p-channel devices, with carrier mobilities of more than 150 and 80 cm2/V s, respectively, and leakage currents of less than 2×10−14 A/μm. From a study of static irradiations, using a semi-Gaussian laser beam, the results are shown to be consistent with the super lateral grain growth (SLG) model. The trailing edge of the beam, when used in a swept mode, has been demonstrated to play an important role in extending the size of the energy window for this effect by re-setting the material into the SLG regime.

An investigation of laser annealed and metal-induced crystallized polycrystalline silicon thin-film transistors

We report results on thin-film transistors (TFTs) made from a new hybrid process in which amorphous silicon (a-Si) is first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (MILC), and then improved using excimer laser annealing (laser MILC or L-MILC). With only a very low shot laser process, we demonstrate that laser annealing of MILC material can improve the electron mobility from 80 to 170 cm/sup 2//Vs, and decrease the minimum leakage current by one to two orders of magnitude at a drain bias of 5 V. Similar trends occur for both p- and n-type material. A shift in threshold voltage upon laser annealing indicates the existence of a net positive charge in Ni-MILC material, which is neutralised upon laser exposure. The MILC material in particular exhibits a very high generation state density of /spl sim/10/sup 19/ cm/sup -3/ which is reduced by an order of magnitude in L-MILC material. The gate and drain field dependences of leakage current indicate that the leakage current in MILC transistors is related to this high defect level and the abruptness of the channel/drain junction. This can be improved with a lightly doped drain (LDD) implant, as in other poly-Si transistors.

Analysis of Drain Field and Hot Carrier Stability of Poly-Si Thin Film Transistors

Hot carrier instabilities in poly-Si thin film transistors (TFTs) are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n+ doping profile in the drain and the two-dimensional (2D) coupling of the x and y components of the electric field between the gate and drain. The density of trapping states in the poly-Si film, however, has a much less significant impact on the field. Further, it is shown that improving the properties of the poly-Si film tends to have an adverse affect on hot carrier stability. Consequently, it is concluded that drain field relief is essential for hot carrier stability of n-channel poly-Si TFTs. It is shown that gate overlapped lightly doped drain (GOLDD) architectures can be used to relieve the drain field without introducing series resistance. Stable TFTs have been fabricated with GOLDD, consistent with circuit operation up to drain biases of 20 V. GOLDD is also effective in reducing the field enhanced leakage current in the off-state.

The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process

The fabrication and optimization of poly-Si thin-film transistors and memory devices on glass substrates at temperatures of 200/spl deg/C-400/spl deg/C is described, and the device characteristics and stability are discussed. The devices were formed using PECVD amorphous silicon, silicon dioxide, and silicon nitride films, and the crystallization of the amorphous silicon was achieved with an excimer laser. The performance of 16/spl times/16 EEPROM arrays with integrated drive circuits formed using this technology is presented.

Laser crystallised poly-Si TFTs for AMLCDs

Abstract The technology for the fabrication of poly-Si TFTs on glass substrates has now reached a level of maturity such that the first commercial products are becoming available. The technology choice will be briefly reviewed and the reasons for the preferred use of excimer laser crystallisation will be summarised. Some of the key device and technology issues will be reviewed in this paper, including the role of the incident laser energy density in fabricating high performance TFTs and its dependence on film thickness. The issues discussed above have determined our design and fabrication of poly-Si AMLCDs and the results obtained from a 2-inch array, with full drive circuit integration, are illustrated.

Thin-film-transistor- and diode-addressed AMLCDs on polymer substrates

Abstract— Amorphous-silicon-rich nitride (αSiNx:H) thin-film diodes (TFDs) have been fabricated on glass, polyethersulphone (PES), polyacrylate (PAR), and polyethelyenenaphthalate (PEN) substrates at temperatures of 150–200°C, and a TFD-addressed TN-LCD fabricated on polyethersulphone is presented. Furthermore, poly-Si thin-film-transistors (TFTs) have been fabricated on glass, polyimide (PI), and polyethersulphone at temperatures of 200–275°C, and active-matrix arrays with drive circuitry have been realized. This work is an important step leading to a compact, lightweight, robust, system on a panel.

54.2: Thin Plastic Electrophoretic Displays Fabricated by a Novel Process

We have developed a new way of making flexible, plastic active matrix displays using standard amorphous silicon TFT fabrication facilities. Using this technique we have made electrophoretic displays with three micron thick plastic a-Si TFT backpanes. We believe that these are the thinnest plastic displays ever made.

Low Temperature Poly-Si on Flexible Polymer Substrates for Active Matrix Displays and Other Applications

A variety of polymer materials including polyimide (PI), polyarylate (PAR), polynorbonene (PNB) and polyethersulphone (PES) have been studied for use as substrates in the formation of active matrix displays based upon polycrystalline silicon (poly-Si) thin film transistors (TFTs). A process used to fabricate transflective mobile phone displays at 250°C on such substrates is described in detail. The NMOS TFTs show a mobility of 100cm 2 /Vs, and a threshold voltage of 3.9V; the PMOS devices have a mobility of 52cm 2 /Vs, and a threshold voltage of -6V. Issues relating to performance of these devices, yield of the arrays, and manufacturability are discussed.