Michael J. Trainor

Influence of melt depth in laser crystallized poly-Si thin film transistors

The influence of film thickness and incident excimer laser energy density on the properties of poly-Si thin film transistors has been investigated and a coherent pattern of behavior has been identified which establishes controlled melt-through of the film as a key condition for achieving high quality devices. The conditions were correlated with the appearance of large grains and gave consistent results from both n- and p-channel devices, with carrier mobilities of more than 150 and 80 cm2/V s, respectively, and leakage currents of less than 2×10−14 A/μm. From a study of static irradiations, using a semi-Gaussian laser beam, the results are shown to be consistent with the super lateral grain growth (SLG) model. The trailing edge of the beam, when used in a swept mode, has been demonstrated to play an important role in extending the size of the energy window for this effect by re-setting the material into the SLG regime.

Efficiency Enhancement of InP Nanowire Solar Cells by Surface Cleaning

We demonstrate an efficiency enhancement of an InP nanowire (NW) axial p-n junction solar cell by cleaning the NW surface. NW arrays were grown with in situ HCl etching on an InP substrate patterned by nanoimprint lithography, and the NWs surfaces were cleaned after growth by piranha etching. We find that the postgrowth piranha etching is critical for obtaining a good solar cell performance. With this procedure, a high diode rectification factor of 10(7) is obtained at ±1 V. The resulting NW solar cell exhibits an open-circuit voltage (Voc) of 0.73 V, a short-circuit current density (Jsc) of 21 mA/cm(2), and a fill factor (FF) of 0.73 at 1 sun. This yields a power conversion efficiency of up to 11.1% at 1 sun and 10.3% at 12 suns.

An investigation of laser annealed and metal-induced crystallized polycrystalline silicon thin-film transistors

We report results on thin-film transistors (TFTs) made from a new hybrid process in which amorphous silicon (a-Si) is first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (MILC), and then improved using excimer laser annealing (laser MILC or L-MILC). With only a very low shot laser process, we demonstrate that laser annealing of MILC material can improve the electron mobility from 80 to 170 cm/sup 2//Vs, and decrease the minimum leakage current by one to two orders of magnitude at a drain bias of 5 V. Similar trends occur for both p- and n-type material. A shift in threshold voltage upon laser annealing indicates the existence of a net positive charge in Ni-MILC material, which is neutralised upon laser exposure. The MILC material in particular exhibits a very high generation state density of /spl sim/10/sup 19/ cm/sup -3/ which is reduced by an order of magnitude in L-MILC material. The gate and drain field dependences of leakage current indicate that the leakage current in MILC transistors is related to this high defect level and the abruptness of the channel/drain junction. This can be improved with a lightly doped drain (LDD) implant, as in other poly-Si transistors.

Analysis of Drain Field and Hot Carrier Stability of Poly-Si Thin Film Transistors

Hot carrier instabilities in poly-Si thin film transistors (TFTs) are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n+ doping profile in the drain and the two-dimensional (2D) coupling of the x and y components of the electric field between the gate and drain. The density of trapping states in the poly-Si film, however, has a much less significant impact on the field. Further, it is shown that improving the properties of the poly-Si film tends to have an adverse affect on hot carrier stability. Consequently, it is concluded that drain field relief is essential for hot carrier stability of n-channel poly-Si TFTs. It is shown that gate overlapped lightly doped drain (GOLDD) architectures can be used to relieve the drain field without introducing series resistance. Stable TFTs have been fabricated with GOLDD, consistent with circuit operation up to drain biases of 20 V. GOLDD is also effective in reducing the field enhanced leakage current in the off-state.

Laser crystallised poly-Si TFTs for AMLCDs

Abstract The technology for the fabrication of poly-Si TFTs on glass substrates has now reached a level of maturity such that the first commercial products are becoming available. The technology choice will be briefly reviewed and the reasons for the preferred use of excimer laser crystallisation will be summarised. Some of the key device and technology issues will be reviewed in this paper, including the role of the incident laser energy density in fabricating high performance TFTs and its dependence on film thickness. The issues discussed above have determined our design and fabrication of poly-Si AMLCDs and the results obtained from a 2-inch array, with full drive circuit integration, are illustrated.

Control and analysis of leakage currents in poly‐Si thin‐film transistors

Control of leakage current in autoregistered columnar and a solid phase crystallized poly‐Si thin‐film transistors (TFTs) is discussed. For n‐channel TFTs, two parasitic leakage current paths, due to bulk conduction and back interface conduction, have been identified. It is demonstrated that these can be controlled by using sufficiently thin films and by low dose boron back channel implants, respectively. By these means, generation limited leakage currents, with values of <4×10−14 A/μm of channel width, have been obtained. The minimum leakage currents, for n‐ and p‐channel TFTs, display the well‐known field enhancement which we confirm can be described by phonon assisted tunneling. In well‐engineered TFTs, with subthreshold slopes of <1 V/dec, we show that the drain fields required to promote the tunneling process are independent of the trap state density and result entirely from two‐dimensional gate‐drain coupling effects. Therefore, improving the quality of the poly‐Si will not reduce the exponential de...

Passive and active matrix addressed polymer light-emitting diode displays

Polymer LEDs provide a new alternative to LCDs for many display applications, and are particularly attractive because of their high brightness, near-perfect viewing angle, and very fast response time. In this paper, the basic technology used to form the LED structures, and the performance of these devices is presented. Then, the fabrication and driving of passive addressed matrix displays formed using this technology is discussed. Finally, the necessity for active matrix addressing for larger size and higher resolution displays is demonstrated, and it is shown that this is best achieved using low temperature poly-Si technology. The state-of-the-art poly-Si technology used for active matrix addressed LED displays is described, with particular reference to transistor variation, and the resulting non-uniformities in images on displays. A variety of different addressing techniques, and pixel circuits can be used to drive the LEDs in the active matrix, and the performances of these schemes are compared. These include the basic current source circuit; the modified current source circuit; transistor current mirror circuits; and circuits with optical feedback and correction for uniformity variation. Consideration is given both to analogue and to digital drive methods.

Intrinsic Gain in Self-Aligned Polysilicon Source-Gated Transistors

Thin-film self-aligned source-gated transistors (SGTs) have been made in polysilicon. The very high output impedance of this type of transistor makes it suited to analog circuits. Intrinsic voltage gains of greater than 1000 have been measured at particular drain voltages. The drain voltage dependence of the gain is explained based on the device physics of the SGT and the fact that a pinchoff occurs at both the source and the drain. The results obtained from these devices, which are far from optimal, suggest that, with a proper design, the SGT is well suited to a wide range of analog applications.

Low Temperature Poly-Si on Flexible Polymer Substrates for Active Matrix Displays and Other Applications

A variety of polymer materials including polyimide (PI), polyarylate (PAR), polynorbonene (PNB) and polyethersulphone (PES) have been studied for use as substrates in the formation of active matrix displays based upon polycrystalline silicon (poly-Si) thin film transistors (TFTs). A process used to fabricate transflective mobile phone displays at 250°C on such substrates is described in detail. The NMOS TFTs show a mobility of 100cm 2 /Vs, and a threshold voltage of 3.9V; the PMOS devices have a mobility of 52cm 2 /Vs, and a threshold voltage of -6V. Issues relating to performance of these devices, yield of the arrays, and manufacturability are discussed.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.