Minjae Lee

A Design of a 92.4% Efficiency Triple Mode Control DC–DC Buck Converter With Low Power Retention Mode and Adaptive Zero Current Detector for IoT/Wearable Applications

This paper presents a retention/ pulse frequency modulation (PFM)/ pulse width modulation (PWM) mode dc–dc buck converter with adaptive zero current detector (AZCD) and spread spectrum clock generation (SSCG) for IoT/Wearable systems. The proposed dc–dc buck converter is capable of handling loads from 10 μA to 20 mA with high efficiency by applying triple mode (retention mode, PFM mode, and PWM mode), gate split technique, and AZCD. Retention mode is proposed to extend wide load range at ultralight load. Gate split technique adjusts the conduction loss and switching loss. AZCD reduces the operation duty of the high-speed comparator and avoid reverse current below light load. In IoT applications, each node communicates with other nodes through a Bluetooth low energy transceiver, which consumes very low current and is highly sensitive to supply noise. Therefore, the proposed dc–dc buck converter adopts the SSCG technique to reduce electromagnetic interference by up to 18 dB. This chip is implemented using 0.13 μm CMOS technology with an active area of

A Triple-Mode Wireless Power-Receiving Unit With 85.5% System Efficiency for A4WP, WPC, and PMA Applications

\text{820}\times \text{800}\;\mu \text{m}^{2}

Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process

. The maximum power efficiency of the proposed dc–dc buck converter is 92.4% at a switching frequency of 2.5 MHz when the load current range is 10 to 20 mA. The input voltage range and the regulated output voltage are 2.2–3.3 and 1.7 V, respectively. In addition, the proposed dc–dc buck converter achieves over 74.2% efficiency in retention mode when the load current range is from 10 to 500 μA.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

This paper presents the design of a triple-mode wireless power-receiving unit (TWPRU) for battery charger with high efficiency. The TWPRU is proposed based on Alliance for Wireless Power (A4WP), Wireless Power Consortium (WPC), and Power Matters Alliance (PMA) standards. An adaptive alignment gate controller technique is proposed in the triple-mode active rectifier to block the reverse leakage current and improve the power conversion efficiency (PCE). This technique can compensate for the delays in the gate control signals of the main switching mosfets at different operating frequencies for A4WP, WPC, and PMA. The dead time of a dc–dc converter is optimally determined depending on the voltage and the temperature variations by phase calibration circuit. This chip with an active area of 5.0 mm × 3.5 mm is implemented in 0.18-μm BCD technology. The maximum PCEs of the triple-mode active rectifier are 91.7% in the A4WP mode and 92.7% in the WPC/PMA mode, respectively. The maximum PCE of the dc–dc converter is 92.3% at a load current of 500 mA, while the system efficiencies of TWPRU at A4WP and WPC/PMA modes are about 84.5% and 85.5%, respectively.

A High Noise Immunity, 28 × 16-Channel Finger Touch Sensing IC Using OFDM and Frequency Translation Technique

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

A 12 bit 250MS/s 28mW +70dB SFDR non-50% RZ DAC in 0.11źm CMOS using controllable RZ window for wireless SoC integration

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of −16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration

In this paper, a high noise immunity, 28 × 16-channel finger touch sensing IC for an orthogonal frequency division multiplexing (OFDM) touch sensing scheme is presented. In order to increase the signal-to-noise ratio (SNR), the OFDM sensing scheme is proposed. The transmitter (TX) transmits the orthogonal signal to each channels of the panel. The receiver (RX) detects the magnitude of the orthogonal frequency to be transmitted from the TX. Due to the orthogonal characteristics, it is robust to narrowband interference and noise. Therefore, the SNR can be improved. In order to reduce the noise effect of low frequencies, a mixer and high-pass filter are proposed as well. After the noise is filtered, the touch SNR attained is 60 dB, from 20 dB before the noise is filtered. The advantage of the proposed OFDM sensing scheme is its ability to detect channels of the panel simultaneously with the use of multiple carriers. To satisfy the linearity of the signal in the OFDM system, a high-linearity mixer and a rail-to-rail amplifier in the TX driver are designed. The proposed design is implemented in 90 nm CMOS process. The SNR is approximately 60 dB. The area is 13.6 mm2, and the power consumption is 62.4 mW.

Energy-efficient switching scheme for SAR ADC using zero-energy dual capacitor switching

A 12-bit current-steering digital-to-analog converter (DAC) in 0.11źm CMOS technology is presented for one DAC with a flexible swing and common-mode voltage for both an IQ baseband wireless transmitter (TX) and an envelope tracking (ET) power amplifier that require low power consumption. The conventional half clock period return-to-zero (RZ) effectively eliminates the code-dependent transient but results in amplitude loss and larger DAC images. The proposed RZ flip-flop generates a controllable RZ signal with a clock duty cycle that is less than 50%, which mitigates such a signal power loss and relaxes the image filtering requirement. In addition, this DAC can easily switch between non-return-to-zero (NRZ) mode and RZ mode to serve various applications. The implemented DAC is character -ized at the sample frequency of 250MHz and it achieves a spurious-free dynamic range (SFDR) greater than 70dB up to the Nyquist frequency. The core area of the DAC is 0.117mm2 and it dissipates about 28mW under a 2.5V supply.

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

A 12 bit CMOS current-steering digital-to-analog converter (DAC) in 0.11 μm CMOS technology is presented for IQ baseband wireless transmitter and envelop tracking (ET) power amplifier that requires low power consumption with flexible swing and common-mode controls. The conventional half clock period return-to-zero (RZ) effectively eliminates code-dependent transient but results in amplitude loss. The proposed controllable RZ window less than 50 % of clock duty cycle mitigates such signal loss, and yet achieves the spurious-free dynamic range (SFDR) better than 70 dB up to Nyquist bandwidth at the sample frequency of 250 MHz. The core area of DAC is 0.117 mm2 and it dissipates about 28 mW under 2.5 V supply.