David M. Binkley

A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under /spl plusmn/0.20 LSB and INL less than /spl plusmn/0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

A CAD methodology for optimizing transistor current and sizing in analog CMOS design

A computer-aided design (CAD) methodology for optimizing MOS transistor current and sizing is presented where drain current ID, inversion level (represented by inversion coefficient IC), and channel length L are selected as three independent degrees of design freedom resulting in an optimized selection of channel width for layout. At a given drain current I/sub D/ in saturation, a selected MOS inversion coefficient IC and channel length L define a point on an operating plane illustrating dramatic tradeoffs in circuit performance. Operation in the region of low inversion coefficient IC and long channel length L results in optimal DC gain and matching compared to the region of high inversion coefficient IC and short channel length L where bandwidth is optimal. A design methodology is presented here to enable optimum design choices throughout the continuum of inversion level IC (weak, moderate, or strong inversion) and available channel length L. The methodology is implemented in a prototype CAD system where a graphical view permits the designer to explore optimum tradeoffs against preset goals for circuit transconductance g/sub m/, output conductance g/sub ds/, drain-source saturation voltage, gain, bandwidth, white and flicker noise, and DC matching for a 0.5-/spl mu/m CMOS process. The design methodology can be readily extended to deeper submicron MOS processes through linkage to the EKV or BSIM3 MOS models or custom model equations.

A power efficient, low noise, wideband, integrated CMOS preamplifier for LSO/APD PET systems

A power-efficient, low-noise, wideband, 0.8-/spl mu/ CMOS charge-sensitive preamplifier has been designed and optimized for LSO/APD based PET systems. Low-noise, wideband performance is needed to achieve 1-ns FWHM timing resolution available from LSO/APD detectors, and power efficiency is needed since thousands of preamplifiers are required in a LSO/APD based PET tomograph. A methodology for optimizing wideband timing performance is presented to minimize dominant, frequency-turn-up, input-noise current associated with input noise voltage and total capacitance at the input. The methodology suggests the use of a nMOS input device operating in moderate inversion for high transconductance and low input white-noise voltage consistent with moderate input capacitance. Measured preamplifier input-referred, white-noise voltage is 0.65 nV//spl radic/(Hz) and risetime is 6 ns (58 MHz 3-dB bandwidth). Measured timing resolution is 1.17 ns FWHM and energy resolution is 18% FWHM for 511-keV gamma rays detected by a 4/spl times/4/spl times/10 mm LSO crystal coupled to an APD. Measurements include the APD capacitance of 30-pF and are obtained at a preamplifier input-device current of only 2 mA.

Performance of non-delay-line constant-fraction discriminator timing circuits

The delay line in the constant-fraction discriminator (CFD) can be replaced with circuit networks to permit monolithic fabrication. The previously reported non-delay-line CFD utilizing a single-pole highpass filter is reviewed, followed by a presentation of non-delay-line circuits utilizing Gaussian lowpass filters. Circuit response for non-delay-line CFDs utilizing single-pole highpass or single-pole lowpass filters is shown to be equivalent. However, timing-signal underdrive and zero-crossing slope are increased and timing jitter reduced when higher-order lowpass filters are used. Comparisons of non-delay-line and delay-line CFD circuit timing performance are presented for lowpass-filtered step inputs representative of scintillation detector signals. Timing resolution of non-delay-line and delay-line CFDs is compared for BGO/photomultiplier scintillation detector applications. Monte Carlo simulations indicate that comparable timing resolution is available with proper selection of non-delay-line CFD filter time-constants. A fully-monolithic CMOS, non-delay-line CFD was fabricated to experimentally validate timing resolution. The measured timing resolution of 3.26 ns FWHM and 6.5 ns FWTM is in good agreement with measured resolution of 3.30 ns FWHM and 6.4 ns FWTM for a standard delay-line CFD circuit. >

Design-oriented characterization of CMOS over the continuum of inversion level and channel length

A methodology for small signal characterization of CMOS processes over the full range of inversion level and channel length is presented. Measured transconductance and output conductance of a 0.5 /spl mu/m standard CMOS process are presented from deep weak inversion to deep strong inversion for both NMOS and PMOS devices for channel lengths ranging from 0.5 /spl mu/m to 33.4 /spl mu/m. The data is presented in normalized form permitting device evaluation at any inversion level, channel length, and drain current. This characterization is useful for modern analog CMOS design anywhere in the continuum of inversion level and channel length. This method furthermore presents a novel and rigorous benchmark for evaluating the accuracy of compact MOS models. Initial results are given illustrating EKV MOS model transconductance accuracy. The characterization methodology can be extended to deeper submicron processes addressing the increasing uncertainty in small signal parameter values and MOS model accuracy.

A custom mixed-signal CMOS integrated circuit for high performance PET tomograph front-end applications

A custom mixed-signal CMOS integrated circuit has been developed for high performance PET tomograph front-end applications. The ASIC contains four differential, variable-gain, constant bandwidth, amplifiers to receive buffered PMT voltage pulses. All four amplified PMT signals are summed by adding their outputs and feeding this sum to the timing channel of the ASIC. The timing channel, which consists of a constant fraction discriminator and sub-nanosecond time to digital converter, offers excellent PET count rate performance and random noise reduction through low deadtime (100 ns) and excellent tuning resolution (312.5 ps). Amplified PMT signals are also distributed to energy processing channels for lowpass filtering, and buffering for subsequent digitization by external ADCs. The ASIC offers substantial size, power, and cost reductions over existing PET front-end discrete designs. Fabricated in a 5 V, 0.5 /spl mu/m, triple metal, double poly, n-well CMOS process, the new ASIC has a die size of 20 mm/sup 2/ and dynamic power dissipation under 425 mW.

Performance characteristics of a new generation of processing circuits for PET applications

An electronics architecture for a PET tomograph is presented which utilizes a newly developed ASIC CFD and TDC to fully utilize the timing advantages of an LSO scintillation crystal. Intrinsic timing resolution for LSO against plastic has been measured at 900 ps FWHM using the ASIC CFDs and TDCs for both channels. The energy and pixel location are derived using continuous sampling ADCs with FPGA digital processing algorithms. Digitally converted PMT signals are modified using dynamic TDC values to recalibrate the energy and position since the sampling frequency is unrelated to the event data. The linearity of the energy channels is 1.8% for a 6:1 input dynamic range.

Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 /spl mu/m CMOS process and implications for analog circuit design

A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.

A low-noise, wideband, integrated CMOS transimpedance preamplifier for photodiode applications

A low-noise, wideband, integrated CMOS transimpedance preamplifier is presented for silicon avalanche photodiode (APD) applications. The preamplifier, fabricated in a standard 2- mu CMOS technology, features a transimpedance gain of 45 k Omega , a risetime of 22 ns, a series noise of 1.6 nV/Hz/sup 1/2/, and a wideband equivalent input-noise current of 12 nA for a source capacitance of 12 pF. The measured /sup 22/Na timing resolution of 9.2-ns full width at half maximum (FWHM) and energy resolution of 22.4% FWHM for the RCA C30994 BGO/APD detector module coupled to the preamplifier are comparable to the performance reported using charge-sensitive preamplifiers. This shows that transimpedance preamplifiers should be considered for APD applications, especially where APD noise current dominates noise from feedback resistors in the 10-k Omega to 50-k Omega range. The transimpedance preamplifier reported here offers advantages of being fully monolithically integrated, having low power dissipation (38 mW), having low bandwidth sensitivity to source capacitance, requiring no shaping-amplifier pole-zero compensation, and requiring no feedback capacitance reset at high count rates.<<ETX>>