James M. Rochelle

A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under /spl plusmn/0.20 LSB and INL less than /spl plusmn/0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.

Multiple-input microcantilever sensors

A surface-micromachined micro-electro-mechanical-system (MEMS) process has been used to demonstrate multiple-input chemical sensing using selectively coated cantilever arrays. Cantilever motion due to absorption-induced stress was readout using a custom-designed, eight-channel integrated circuit. Combined hydrogen and mercury vapor detection was achieved with a palm-sized, self-powered module with spread-spectrum telemetry reporting.

A CAD methodology for optimizing transistor current and sizing in analog CMOS design

A computer-aided design (CAD) methodology for optimizing MOS transistor current and sizing is presented where drain current ID, inversion level (represented by inversion coefficient IC), and channel length L are selected as three independent degrees of design freedom resulting in an optimized selection of channel width for layout. At a given drain current I/sub D/ in saturation, a selected MOS inversion coefficient IC and channel length L define a point on an operating plane illustrating dramatic tradeoffs in circuit performance. Operation in the region of low inversion coefficient IC and long channel length L results in optimal DC gain and matching compared to the region of high inversion coefficient IC and short channel length L where bandwidth is optimal. A design methodology is presented here to enable optimum design choices throughout the continuum of inversion level IC (weak, moderate, or strong inversion) and available channel length L. The methodology is implemented in a prototype CAD system where a graphical view permits the designer to explore optimum tradeoffs against preset goals for circuit transconductance g/sub m/, output conductance g/sub ds/, drain-source saturation voltage, gain, bandwidth, white and flicker noise, and DC matching for a 0.5-/spl mu/m CMOS process. The design methodology can be readily extended to deeper submicron MOS processes through linkage to the EKV or BSIM3 MOS models or custom model equations.

Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells.

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit.

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal processing is accomplished with a current-to-frequency converter circuit that forms the causal portion of the matched filter for dc luminescence in wide-band white noise. Measurements show that luminescence can be detected from as few as 4 x 10(5) cells/ml.

A custom mixed-signal CMOS integrated circuit for high performance PET tomograph front-end applications

A custom mixed-signal CMOS integrated circuit has been developed for high performance PET tomograph front-end applications. The ASIC contains four differential, variable-gain, constant bandwidth, amplifiers to receive buffered PMT voltage pulses. All four amplified PMT signals are summed by adding their outputs and feeding this sum to the timing channel of the ASIC. The timing channel, which consists of a constant fraction discriminator and sub-nanosecond time to digital converter, offers excellent PET count rate performance and random noise reduction through low deadtime (100 ns) and excellent tuning resolution (312.5 ps). Amplified PMT signals are also distributed to energy processing channels for lowpass filtering, and buffering for subsequent digitization by external ADCs. The ASIC offers substantial size, power, and cost reductions over existing PET front-end discrete designs. Fabricated in a 5 V, 0.5 /spl mu/m, triple metal, double poly, n-well CMOS process, the new ASIC has a die size of 20 mm/sup 2/ and dynamic power dissipation under 425 mW.

Performance characteristics of a new generation of processing circuits for PET applications

An electronics architecture for a PET tomograph is presented which utilizes a newly developed ASIC CFD and TDC to fully utilize the timing advantages of an LSO scintillation crystal. Intrinsic timing resolution for LSO against plastic has been measured at 900 ps FWHM using the ASIC CFDs and TDCs for both channels. The energy and pixel location are derived using continuous sampling ADCs with FPGA digital processing algorithms. Digitally converted PMT signals are modified using dynamic TDC values to recalibrate the energy and position since the sampling frequency is unrelated to the event data. The linearity of the energy channels is 1.8% for a 6:1 input dynamic range.

Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 /spl mu/m CMOS process and implications for analog circuit design

A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.

A low-noise, wideband, integrated CMOS transimpedance preamplifier for photodiode applications

A low-noise, wideband, integrated CMOS transimpedance preamplifier is presented for silicon avalanche photodiode (APD) applications. The preamplifier, fabricated in a standard 2- mu CMOS technology, features a transimpedance gain of 45 k Omega , a risetime of 22 ns, a series noise of 1.6 nV/Hz/sup 1/2/, and a wideband equivalent input-noise current of 12 nA for a source capacitance of 12 pF. The measured /sup 22/Na timing resolution of 9.2-ns full width at half maximum (FWHM) and energy resolution of 22.4% FWHM for the RCA C30994 BGO/APD detector module coupled to the preamplifier are comparable to the performance reported using charge-sensitive preamplifiers. This shows that transimpedance preamplifiers should be considered for APD applications, especially where APD noise current dominates noise from feedback resistors in the 10-k Omega to 50-k Omega range. The transimpedance preamplifier reported here offers advantages of being fully monolithically integrated, having low power dissipation (38 mW), having low bandwidth sensitivity to source capacitance, requiring no shaping-amplifier pole-zero compensation, and requiring no feedback capacitance reset at high count rates.<<ETX>>

A low-noise, wide-band CMOS charge-sensitive preamplifier for use with APD/LSO PET detectors

The recent emergence of LSO as a potential scintillator for positron emission tomography (PET) and recent improvements in avalanche photodiode (APD) technology offer encouragement that an APD/LSO based PET detector may be commercially viable in the near future. An important component of any APD/LSO based PET detector will be the preamplifier used to read out the low-level detector signals. Due to the large number of detectors (>18,000) in a high-resolution PET scanner, the preamplifier must be implemented as a monolithic integrated circuit. Additionally, in order to achieve the timing resolution required for high resolution PET, the preamplifier must have a large band-width and a low equivalent input noise voltage. This paper presents a CMOS charge-sensitive preamplifier design which uses local feedback to improve the performance of the common gate transistor. The modified cascode circuit is analyzed and compared with a previously reported simple folded cascode circuit. A prototype circuit was fabricated in a 2 /spl mu/m NWELL CMOS process. The prototype amplifier has a measured 10-90% rise-time of 7 ns with an external input capacitance of /spl sim/6 pF and has an equivalent input noise voltage of /spl sim/1.1 nV/rt-Hz above the flicker noise corner. A pulse height resolution of 14.3% FWHM and a timing resolution of 1.57 ns FWHM (vs. plastic) were obtained with the preamplifier, an Advanced Photonix 5 mm diameter beveled-edge APD and 3.5/spl times/3.5/spl times/22 mm/sup 3/ Teflon wrapped LSO crystal.