David Onsongo

Mobility enhancement in surface channel SiGe PMOSFETs with HfO 2 gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.

Employing Step-and-Flash imprint lithography for gate-level patterning of a MOSFET device

Step and Flash Imprint Lithography (SFIL) is an alternative lithography technique that enables patterning of sub-100 nm features at a cost that has the potential to be substantially lower than either conventional projection lithography or proposed next generation lithography techniques. SFIL is a molding process that transfers the topography of a rigid transparent template using a low-viscosity, UV-curable organosilicon solution at room temperature and with minimal applied pressure. Employing SFIL technology we have successfully patterned areas of high and low density, semi-dense and isolated lines down to 20 nm, and demonstrated the capability of layer-to-layer alignment. We have also confirmed the use of SFIL to produce functional optical devices including a micropolarizer array consisting of orthogonal 100 nm titanium lines and spaces fabricated using a metal lift-off process. This paper presents a demonstration of the SFIL technique for the patterning of the gate level in a functional MOSFET device.

Simulation and optimization of strained Si1−xGex buried channel p-MOSFETs

Abstract Deep submicron (0.35 μm) strained Si1−xGex buried channel p-MOSFETs with a Ge concentration up to 50% were simulated using the MEDICI device simulator. A buried channel structure offers several benefits over a surface channel structure without a Si cap. Simulation results show that the maximum drain current increases monotonically with the Ge mole fraction. The drive current enhancement is more than 300% for Si0.5 Ge0.5 over Si. Subthreshold characteristics were analyzed for different Ge mole fractions in this study. The effects of Si cap layer thickness and Si1−xGex channel thickness on drive current and gate voltage operating window were analyzed. The simulation results show that the drive current is the highest when the Si1−xGex layer thickness is between 100 and 300 A and that Si1−xGex layer thickness can be as low as 50 A with less than 10% penalty in the drive current, for structures with a 50 A Si cap layer.

Low-frequency noise in SiGeC-based pMOSFETs

The SiGeC ternary alloy seems to be an attractive material system for Si-based device applications, because the incorporation of a small amount of C in the high-mobility SiGe layer offers an additional degree of freedom for tuning the bandgap, band offsets and the lattice strain in group IV heterostructures. In this work, detailed low-frequency noise (LFN) results in SiGeC pMOSFETs are presented. Our experimental results in saturation regime of the SiGe MOSFET show that the noise in SiGeC MOSFETs at gate bias |VGS-VT|<0.4V can be referred to the gate terminal as a noise voltage SVG=VG2, which implies (ΔN) fluctuation with correlated noise in the cap and SiGeC channel currents. Overall, the trend shows that the gate referred noise voltage scales inversely with the gate area, and that the variation of the noise level has log-normal distribution. Therefore, the noise in SiGeC MOSFETs can be expressed as S=Savg*exp(t*σNp), where t=±1,...,±3 is a coefficient selected for desired confidence probability of 0.6,...,0.99 respectively, and σ is the standard deviation of the log-normal distribution of the noise level around its average Savg, later given by (ΔN-Δμ) fluctuation in the cap layer and SiGeC channel of pMOSFET.

SiGe heterojunction vertical p-type metal–oxide–semiconductor field-effect transistors with Si cap

SiGe source heterojunction p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) have been used before to suppress the short channel effect for sub-100 nm devices. While the leakage is reduced, the drive current is also reduced due to the heterojunction. In this letter, we discuss a SiGe source heterojunction vertical p-MOSFET with a few nanometers thick Si cap. With this device structure, the absence of the heterojunction-induced potential barrier right below the oxide interface improves the drive current substantially while the drain induced barrier lowering (DIBL) effect and floating body effect are still suppressed. The electrical characterization of the device shows it exhibits higher drive current and less DIBL compared with a Si control device.