David Secker

Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

This paper presents a double-sided flip-chip package. The package consists of a memory controller on one side of an organic substrate, and 3D-stacked, disaggregated memory chips, integrated with TSVs, on the opposite side. Thermal isolation is one of the key motivations for this configuration. Co-design of all physical layers is required to optimize the integrated 3D package within electrical and manufacturing constraints. Double-sided flip-chip packaging also presents unique challenges in the design of the power delivery network (PDN). A pre-layout design strategy is described, which optimizes the PDN design across 11 power domains to meet stringent impedance targets.

Design and characterization of a high-performance wire-bond ball-grid-array package

The wire-bond ball-grid-array (BGA) package is of interest because of its low cost and high pin counts. For better electrical performance, the coupling in the wire-bond regions needs to be contained. This paper shows a double-swizzle design that reduces coupling by ∼40% from a reference single-swizzle design. The smaller coupling was achieved through the proper assignment of ground wires. Test packages with shorted load were built, and the measurements were done by connecting either a vector network analyzer (VNA) or a time-domain reflectometer (TDR) to the balls of the package. The coupled models of bond wires, fanouts, traces, and plating stubs were then extracted from the measured data by a customized extractor. The extracted models gave some insights into the package. The attenuation was larger than expected. Some spikes in the measured S11 plots were attributed to the coupling. A package model without coupling would not be able to capture these spikes. Yet there were other spikes that were unexplained. They were finally tracked down to be caused by the Vdd plane and routing. Connecting decoupling capacitors between Vdd and ground balls moved the resonance spikes to higher frequencies. Shorting the Vdd and ground balls eliminated these mysterious spikes altogether.

RDRAM/spl reg/ channel design with 32-bit 4.8 GB/s memory modules

This paper describes an RDRAM channel design with novel 32-bit RIMM/spl reg/ modules which deliver a data bandwidth of 4.8 GB/s at 600-MHz clock frequency. Only two RIMM modules are needed for the entire 32-bit, 2-channel design, reducing both the board space and manufacturing cost. Detailed physical architecture, design optimization, and modeling and simulation methodology are presented. Numerous simulations with multi-stage calibration are automated to ensure ample voltage and timing margins for a robust design.

Signal and power integrity analysis of a 256-GB/s double-sided IC package with a memory controller and 3D stacked DRAM

This paper presents signal and power integrity analysis of a double-sided flip-chip package. A memory controller is attached on one side of the organic substrate, and 3D-stacked, disaggregated memory chips, integrated with through silicon vias (TSVs), are connected on the opposite side. The signaling path of this 3D memory system consists of a short channel consisting of wafer-level redistribution layer (RDL) traces and small TSV vias. The signal integrity is not a source of concern for this extremely short channel; power integrity, however, poses significant challenges and consequently can limit the achievable data rate of this system. The double-sided flip-chip packaging p resents unique challenges in the design of l o w-impedance the power delivery network (PDN) and circuit design with low-sensitivity to power supply noises. All physical layers are code sign to optimize the integrated 3D package within electrical and manufacturing constraints in conjunction with robust circuit design that meets the power constraint. The detailed signal integrity analysis is presented to design robust link with low-swing signals and power integrity analysis to optimize the PDN designs to meet the PDN impedance targets.

Design and analysis of 12.8 Gb/s single-ended signaling for memory interface

The design of a high-speed single-ended parallel interface using conventional package and board technologies is presented. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ transactions are on the controller to reduce the memory cost. The analysis and optimization steps employed to mitigate the effect of inter-symbol interference, crosstalk, and supply noise are discussed. The impact of data encoding techniques on system timing margin is also investigated. The designed single-ended signaling was able to achieve a reliable communication at a data rate of 12.8 Gbps over a graphics channel. Several of the noise reduction techniques were also verified with measurement made on a prototype system.

4.0–4.8 Gbps XDR memory channel for graphics intensive consumer applications

A 3.2 Gbps XDR™ memory channel has been optimized to achieve a bit rate of 4.8 Gbps. The 24-bit wide memory interface can deliver an aggregate data bandwidth of 14.4 GB/s to support graphics intensive consumer applications such as high refresh rate 3D digital TV. The optimized high performance channel is also designed to satisfy the low-cost constraint of consumer electronics by using wirebond packaging for the SoC and 4-layer PCB.