Kyung Suk Oh

Multiple Edge Responses for Fast and Accurate System Simulations

High-speed input/output (I/O) link performance is limited by random noise as well as signal integrity issues such as dispersion, reflections, and crosstalk. Hence, accurate prediction of system performance including these random and deterministic noise is crucial in high-speed link design. This paper presents a novel, fast, and accurate method to simulate the time-domain system response. The presented method calculates the system response using multiple edge responses (MER) based on linear superposition. Being able to take into account system nonlinearity more accurately, the presented method significantly improves simulation accuracy compared with the other published fast simulation techniques based on either single bit response (SBR) or double edge responses (DER), while at the same time maintaining equivalent numerical efficiency. Furthermore, peak distortion analysis, which is commonly used to find the worst-case data pattern based on SBR, is extended for DER and MER using dynamic programming. A multiphase worst-case data pattern approach is also introduced in this paper in order to determine the worst-case system performance under both timing and voltage consideration.

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric

A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin. The adaptation strategy is verified in a 90-nm test chip on both the transmitter finite-impulse response filter (Tx-FIR) and the receiver decision-feedback equalizer (Rx-DFE). The performance is compared with the commonly used sign-sign least mean square (SS-LMS) adaptation and demonstrates significant improvements especially in the case of the Tx-FIR. This paper also demonstrates that in a highly attenuating system that contains both a Tx-FIR and Rx-DFE, using a Tx-FIR subject to peak output power constraint to compensate pre-cursor ISI is worse than solely using an Rx-DFE. The adaptation strategy is further applied to adapt the sampling phase of the clock-and-data recovery loop (CDR). The technique enables near-optimal BER performance by substantially reducing the pre-cursor ISI and requires almost no additional hardware compared to SS-LMS adaptation.

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.

Improved method for characterizing transmission lines using frequency-domain measurements

This work presents an improved and accurate methodology for extracting lossy frequency-dependent transmission parameters from S-parameter measurements. The presented technique first uses the multiline method to accurately determine the propagation constant. Then, it proposes a new approach to compute the characteristic impedance by determining the admittance first, based on the fact that the admittance can be modeled as a linear function of frequency. This process ensures both frequency dependent conductor and dielectric losses are accurately determined. It is demonstrated, through several practical examples, that the resulting transmission line parameter is free of common modeling errors at resonant frequencies.

Improving the accuracy of on-chip parasitic extraction

The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified. This paper shows that the generation of accurate capacitance models can be automated with thousands of field-solver simulations and nonlinear regression. The fundamental limitations of LPE tools are discussed. Finally, a 3D Monte-Carlo field solver is used to validate and further improve the LPE results.

Efficient representation of multi-bit data bus structures by symmetric two-line models

This paper presents several methods that model a multi-bit data bus structure by a two-line equivalent. A rigorous approach using formal matrix reduction results in an accurate but asymmetric model which is inconvenient to use in simulating complex systems because the rest of the system needs be adjusted accordingly. Forcing the equivalent two-line model to be symmetric gives the advantage of applying the even- and odd-mode concept, but can lose accuracy in highly coupled lines. A novel approach is shown in this paper to include secondary coupling and achieve an equivalent, symmetric, and accurate two-line model.

RDRAM/spl reg/ channel design with 32-bit 4.8 GB/s memory modules

This paper describes an RDRAM channel design with novel 32-bit RIMM/spl reg/ modules which deliver a data bandwidth of 4.8 GB/s at 600-MHz clock frequency. Only two RIMM modules are needed for the entire 32-bit, 2-channel design, reducing both the board space and manufacturing cost. Detailed physical architecture, design optimization, and modeling and simulation methodology are presented. Numerous simulations with multi-stage calibration are automated to ensure ample voltage and timing margins for a robust design.