Arun Vaidyanath

Design and analysis of a TB/sec memory system

The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the timing adjustment and equalization circuits for both memory WRITE and READ are on the controller to reduce the memory cost. This paper describes the design and analysis employed to develop the memory interface using conventional and low-cost interconnect technologies. The design and characterization of the prototype system at component and system-level are presented and model to hardware correlations are discussed at component and system levels. System analysis is used to optimize and predict the yield of the system, to calculate system timing and voltage margins, and to verify targeted bit-error-rate (BER).

Optimizing the timing center for high-speed parallel buses

As data rates continue to increase, the quality of the transmitted signal is not the only important factor in the design of modern high-speed I/O interfaces; accurate positioning of the receiver clock, in order to detect an incoming signal, is also critical. Modern high-speed I/O interfaces, including both parallel and memory buses (such as Elastic Interface, QuickPath Interconnect, HyperTransport, XDR DRAM, and GDDR5 DRAM buses), already include a data-training feature used to center the receiver clock. This paper describes the general principles used in various timing centering algorithms. Specifically, two different approaches, based on the worst-case eye opening and the median of eye fuzz, are compared. The timing center can drift significantly, due to temperature variation and low frequency supply voltage noise, and consequently requires periodic updates. This paper presents an efficient way to track this timing drift periodically. In mobile applications, some of the low-power modes of operations prohibit the use of the periodic timing calibration to minimize power consumption. A novel scheme to avoid this power consumption is also introduced.

Design of low cost QFP packages for multi-gigabit memory interface

The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the LQFP package leadframes, power integrity is a major challenge for achieving high data rates. While single-ended signaling systems such as DDR and GDDR are very difficult to operate at multi-gigabit data rates using this highly inductive LQFP package, differential signaling systems such as an XDR memory interface is more immune to supply noise and it is suitable for high data rate operations. In this paper, we demonstrate that the XDR memory system with LQFP memory controller package can operate reliably at 3.2Gb/s. The proposed design is achieved by deploying a package/chip co-design approach, and by carefully balancing the supply-noise-induced jitter on different supply rails of the chip. Finally, the system function is validated under a test system with the proposed LQFP package and the model to hardware correlation at system level is presented.

A Novel Package Feasibility Study Tool for Power Delivery Network Design and Optimization

The paper presents a novel package feasibility study tool for package Power Delivery Network (PDN) design and optimization. To capture the loop inductance of various package PDNs, closed-form expressions have been developed for patterned via inductance and plane inductance including regular and irregular plane shapes, which are efficient yet accurate. The closed-form inductance formulas are based on partial self and mutual inductance. The partial inductance matrices are computed according to the via and plane structure dimensions. Then loop inductance can be derived from the order reduction of partial inductance matrices once the current loops are defined. Our tool has been validated through the commercial 3D EM simulator for the typical PDN structures. We also apply our techniques to extract PDNs inductance for a high speed serial link IC package. The time is greatly reduced from hours/days to several minutes while achieving the same order of accuracy as a 3D EM tool.

Impedance Perturbation Theory for Coupled Uniform Transmission Lines

Taking the impedance mismatch of transmission lines as a small quantity, a novel impedance perturbation theory based on the lumped transmission line model is established for both the single-ended and coupled transmission lines. The propagation constant, S-parameters, and T-parameters can be directly constructed from an impedance perturbation factor. As an application example, a detailed perturbation analysis is carried out for differential striplines, which provides insights in the S-parameter features and the splitting in the modal propagation constants. The corresponding numerical simulation indicates that the perturbation model captures and explains the most important features of the exact S-parameters. As another application example, the perturbation model is employed in the through-reflection-line deembedding formulas to evaluate the measurement accuracy and sensitivity. The trends obtained by this analysis is later confirmed by experimental results.

Accuracy tolerance analysis of the multimode TRL de-embedding technique

A perturbation analysis is carried out in the multimode TRL (through-reflection-line) de-embedding formulae to evaluate the accuracy tolerance. The trends obtained by this analysis is confirmed by the corresponding experimental verifications.

Challenges in extending single-ended graphics memory data rates

While the need for higher graphics memory bandwidth continues to grow, it is evident that owing to the multitude of challenges in single ended signaling, pushing data rates beyond 6 Gbps is exceedingly difficult. To isolate, quantify and combat the most important factors that limit the performance of modern high speed single ended systems, a high speed GDDR5 memory system (link width: ×32) has been designed using a Rambus prototype test-chip (TSMC 40 nm process node) and a leading single ended signaling graphics GDDR5 DRAM. Critical challenges faced in scaling the data rates up to 8 Gbps are presented and the varying impact of these challenges on the system margin is shown for increasing speeds. An example of a chip-to-chip system between two prototype test chips, that mitigates these performance limiting determinants, is shown to operate robustly at data rates beyond 8 Gbps. The ingredients of this system are likely techniques for the future graphics memories.

4.0–4.8 Gbps XDR memory channel for graphics intensive consumer applications

A 3.2 Gbps XDR™ memory channel has been optimized to achieve a bit rate of 4.8 Gbps. The 24-bit wide memory interface can deliver an aggregate data bandwidth of 14.4 GB/s to support graphics intensive consumer applications such as high refresh rate 3D digital TV. The optimized high performance channel is also designed to satisfy the low-cost constraint of consumer electronics by using wirebond packaging for the SoC and 4-layer PCB.

Characterization and hardware correlation of multi-gigahertz parallel bus with transmit pre-emphasis equalization

This work describes the characterization and hardware correlation of an equalized parallel bus for multi-gigahertz data-rate operation. In contrast to our earlier paper where interconnect design, modeling, and equalization of band-limited channels were discussed, This work focuses on characterization and correlation methodologies of complete passive and active chip-to-chip communication systems. The simulation and measurement results of equalized channels are correlated in both time and frequency domains. The performance of equalized channels is also verified by comparing the measured and simulated eye diagrams for various values of equalization coefficients up to 8 GHz data rates.