David Trémouilles

Accelerated lifetime test of RF-MEMS switches under ESD stress

This paper presents the results of a study on issues of reliability and accelerated life testing for radio frequency micro-electromechanical system (RF-MEMS) capacitive devices. A human-body-model electrostatic discharge tester has been used to induce charging by operating at stress levels much higher than would be expected in normal use. Temperature ranges from 300 K to 330 K allows the understanding of physical mechanisms that may be responsible for the device’s reliability.

TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

Abstract The number of circuit design iterations due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD and ESD SPICE modeling can be used to solve ESD protection issues in an analog CMOS technology.

Different failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure

The failure signatures of a grounded-base NPN bipolar ESD protection under multiple TLP and HBM stresses are analyzed. For this particular device having a graded collector region, multiple TLP or HBM stresses result in different types of defects. OBIC techniques and TCAD simulations are used to thoroughly analyze the involved physical mechanisms.

Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation

We present a methodology for precise measurements and simulations of ESD system level stress applied to a simple printed circuit board. The impact of an external decoupling capacitance on the ESD propagation paths into an Integrated Circuit (IC) is demonstrated. Resulting current and voltage waveforms are analyzed to highlight the interactions between IC and components (including package, PCB and ESD protections).

Reliability assessment of electrostatically driven MEMS devices: based on a pulse-induced charging technique

The charging mechanism of electrostatically driven MEMS devices was investigated. This paper shows experimental results of (i) electrostatic discharge (ESD) experiments, (ii) charging mechanism modelling and (iii) Kelvin probe force microscopy tests. It highlighted dielectric failure signature occurred under ESD events and allowed understanding of the underlying breakdown mechanism. A further study of the charging effect in conditions below the breakdown was carried out. A new approach to explore trapping phenomena that take place in thin dielectric used for electrostatic actuation is reported. Indeed a pulse-induced charging (PIC) test procedure aimed at reliability assessment of electrostatically actuated MEMS devices is presented. Based on this method, a procedure for carrying out stress testing was defined and successfully demonstrated on capacitive MEMS switches. In this case, high-voltage pulses were applied as stimulus and the parameter Vcapamin, which is directly related to the charging of the insulator layer, was monitored. The PIC stress test results were correlated with conventional cycling stress ones. Finally, temperature-dependent measurements, ranging from 300 up to 355 K, were reported in order to validate the thermal-activated behaviour of the test structures. According to an Arrhenius model, the given reference material showed an activation energy of around 0.77 eV.

Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD).

Abstract High reliability electronic devices need to sustain thousands of electrostatic discharge (ESD) stresses during their lifetime. In this paper, it is demonstrated that repetitive ESD stresses on a protection device such as a bidirectional diode induce progressive defects into the silicon bulk. With “Sirtl etch” failure analysis technique, the defects could be localized quite precisely at the peripheral in/out junctions. The degradation mechanisms during repetitive IEC 61000-4-2 pulses have been investigated on a protection diode with the objective of improving the design for sustaining 1000 pulses at 10xa0kV level.

Analysis of an ESD failure mechanism on a SiC MESFET

Efficient energy management become more and more crucial with increasing energy resource scarcity. Power electronic will play a major role in this field and thus require innovations like using wide band gap semiconductor to build power devices. SiC, GaN, diamond material-based devices are currently more or less mature and will sooner or later require investigations on their reliability to allow their wide adoption. In this work we investigate on the robustness of a SiC-MESFET to ElectroStatic-Discharge (ESD). Surprisingly the ESD robustness is rather low and found to be related to both current non-uniformity and a quite unexpected parasitic NPN bipolar transistor triggering. The outcome of this study allows proposing first guidelines to optimize ESD robustness of such devices.

An electrostatic-discharge-protection solution for Silicon-Carbide MESFET

Among wide band gap material for power electronic, Silicon Carbide (SiC) is the most advanced and starts to gain market shares. We have studied planar SiC MESFET ESD robustness. To solve the problem of their low intrinsic ESD robustness, we demonstrate in this work an effective protection solution and possible improvements.

Failure analysis of ESD-stressed SiC MESFET

Abstract Reliability studies are required for SiC device development. In a previous work we studied the intrinsic ESD robustness of a SiC MESFET. The failure mechanism was related to the triggering of an NPN parasitic transistor. In this work, a new MESFET layout is considered, which optionally include a Zener diode for internal protection. TLP testing and failure analysis has been carried out. Two new failure mechanisms are evidenced. Based on this knowledge, solutions are proposed to further improve the ESD robustness.

Optimization of a MOS–IGBT–SCR ESD protection component in smart power SOI technology

A MOS-IGBT-SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this paper. The drift area, the form factor, and the proportion of P + sections inserted into the drain are the main parameters, which have a significant impact on the latch up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V. 1 Introduction The electrostatic discharge (ESD) has always been one of the highest reliability concerns in the integrated (IC) manufacturing industry. With the continuous miniaturization process, the integrated circuits become more and more vulnerable to ESD. The miniaturization of the ESD protection blocks is one of the greatest challenges of smart power technologies. Silicon On Insulator (SOI) technologies allow extending the operational temperature range while providing the necessary isolation between components with a reduced silicon area. SOI technology is becoming more and more attractive to manage very high voltage blocks, to reduce parasitic NPN effect and to increase Integrated Circuit (IC) speed as well as for applications operating at high temperature [1], [2]. Electro Static Discharge (ESD) protections occupy a significant silicon IC area. Using a LDMOS as main ESD protection component is not optimal due to its high on-resistance, but it could be the only solution for some technologies. In a previous work, we proposed a new ESD component (MOS-IGBT-SCR) and improved it in order to increase ESD performance and improve the latch up immunity [3] [4]. ESD performance was excellent but margin to prevent latch up was not satisfying. In this paper, an optimized version of this structure is discussed and experimentally validated. As the technological parameters of the used technology (TFSMART1: SOI smart power technology) cannot be changed, we explored various layout-design solutions such as the device topology or the architecture. 2 Structure description and preview solution