Nicolas Nolhier

Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

A thorough analysis of the physical mechanisms involved in a vertical grounded-base n-p-n bipolar transistor (VGBNPN) under electrostatic discharge (ESD) stress is first carried out by using two-dimensional (2-D) device simulation, transmission line pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed.

ESD failure signature in capacitive RF MEMS switches.

RF MEMS are commonly known as electrostatic devices using high electric field for their actuation. They can be exposed to transient voltages in any environment, and are very sensitive. According to this point of view, it is necessary to understand and analyze the degradations and failure criteria that can make them useless or reduce their lifetime. This paper deals with the investigation of ESD failure signature in capacitive RF MEMS. ESD experiments were carried out using a transmission line pulsing technique. It has been observed that electrical discharges give rise to sparks or electrical arcing and induced DC parameter shift, which can directly lead to changes in RF metrics. The contact-less dielectric charging effects of ESD pulses have been reported in this paper. It has been found that induced charges are predominant compared to injected ones through the trend of slope of the shift in the voltage corresponding to the minimum of capacitance.

Accelerated lifetime test of RF-MEMS switches under ESD stress

This paper presents the results of a study on issues of reliability and accelerated life testing for radio frequency micro-electromechanical system (RF-MEMS) capacitive devices. A human-body-model electrostatic discharge tester has been used to induce charging by operating at stress levels much higher than would be expected in normal use. Temperature ranges from 300 K to 330 K allows the understanding of physical mechanisms that may be responsible for the device’s reliability.

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

In this paper, we show how latch-up guard rings, surrounding electrostatic discharges (ESD) protection devices, can reduce the overall performance of the ESD protection scheme. This issue is addressed by TCAD simulation and experimental results. Design guidelines to cope with this problem are proposed.

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.

Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

A thorough analysis of the physical mechanisms involved in a vertical grounded-base NPN bipolar transistor (VGBNPN) under ESD stress is first carried out by 2D-device simulation, square pulse measurements (TLP) and photoemission experiments. As a result, we propose a compact model using a new physics-based avalanche formulation. This allows reproduction of the unexpected low value of the VGBNPN snapback holding voltage under TLP stress.

Characterization and modeling methodology for IC’s ESD susceptibility at system level using VF-TLP tester

This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A very fast transmission line pulsing (VF-TLP) tester is used to inject a disturbance into an IC under operation. A system failure criterion is chosen and a critical stress level is extracted. A modeling methodology is also developed to precisely describe each part of the set up and provide a complete model that describes the IC response to ESD indirect effects.

TCAD Methodology for ESD Robustness Prediction of Smart Power ESD Devices

This paper presents a new method to predict the electrostatic-discharge (ESD) protection robustness of a device with technology-in-computer-aided-design (TCAD) simulations. Tested on different devices and two Smart Power technologies, the results are validated through electrical measurement and failure analysis. Failure current is always predicted with a good accuracy compared to technology spreading. In addition, the methodology provides a significant simulation time speedup compared to classical methods based on a temperature criterion

The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation

A methodology for the application of two-dimensional (2-D) device simulation to electrostatic discharge (ESD) events is presented. Correlation of ESD simulation results with experimental data is illustrated using a grounded base n-p-n transistor. It is shown that device simulation is essential for understanding complex ESD failure mechanisms. The application of the methodology to the design of a new ESD protection structure, the mirrored lateral silicon controlled rectifier (MILSCR), is then discussed. Experimental results show that the MILSCR provides a very efficient double-polarity ESD protection. Finally, device simulation is used to optimize this structure for smart-power applications. In particular, holding currents as high as 134 mA are achieved, allowing one to cope with the latchup danger during normal operation.

ESD stress in RF-MEMS capacitive switches: The influence of dielectric material deposition method

The present work investigates the influence of dielectric film deposition method on the charging behavior of RF-MEMS capacitive switches, stressed by electrostatic discharges. A Transmission Line Pulsing generator is used to produce the short transient event. The results show two simplified charging mechanisms influenced by discharges. The comparison between two silicon nitride confirms the effect of the dielectric material deposition method on the reliability of the switches.