Debasis Dawn

A 90nm CMOS 60GHz Radio

CMOS-based circuits operating at mm-wave frequencies have emerged in the past few years. This paper discusses the integration of a 60GHz CMOS single-chip transmitter and a single- chip receiver using a standard 90nm CMOS technology demonstrating a reliable solution for 60GHz single-chip radio. Proper transistor layout, complete and accurate modeling and optimized parasitic extraction method enabled the robust design of the wideband super-heterodyne architecture to support the entire 57- to-66GHz band. The analog radio front-end is controlled by a serial digital interface and has been co-designed and integrated together with a high-speed digital signal processor including analog-to-digital conversion, high speed PHY signal processing such as frequency-offset compensation, phase tracking, FIR and DFE, to support both advanced OFDM and SCBT modulation scheme. The resulting single-chip solution enables data throughputs exceeding 7Gb/s (QPSK) and 15Gb/s (16QAM) for a total DC power budget of below 200mW in TDD operation. In combination with a low-cost FR4-based packaging technology, it provides a high-performance cost-effective solution for a wide range of high volume consumer electronic applications.

60 GHz single-chip 90nm CMOS radio with integrated signal processor

A 60GHz single-chip CMOS radio has been fully integrated using standard 90nm CMOS process technology. The digitally controlled wideband super-heterodyne architecture combined with a high-speed digital signal processor has been designed to support the whole 57 to 66 GHz bandwidth available, and enable data throughput exceeding 7Gbps QPSK and 15Gbps 16QAM for a total DC power budget below 200mW. The receiver chain provides a total gain of nearly 50dB for a total noise figure below 9dB while the power amplifier delivers +8.4dBm saturated output power at 60GHz. The single-chip radio is digitally controlled via a standard SPI, and scalable to a phased array architecture. This is the highest level of integration for a 60GHz single-chip transceiver reported till date. The design has been optimized for robustness against process variation and temperature, and verified by measurement results.

60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity

In this paper, we present four examples of highly integrated 60 GHz single-chip CMOS 90 nm digital radios and phased array solutions. These solutions include for the first time digital-to-analog/analog-to-digital conversion and embedded multi-gigabit mixed signal modem requiring no external processing. This convergence of 60 GHz CMOS digital radio, low power multi-gigabit mixed-signal processing and digital signal processing on a single chip offers the lowest energy per bit transmitted wirelessly at multi-gigabit rate to meet the very stringent low-power specifications for battery operated consumer electronic portable devices. Layout and temperature dependent 60 GHz CMOS 90 nm model development and critical high performance analog and mixed building blocks are presented as fundamental enablers for single chip integration. The designs have been optimized for robustness against process variation and temperature, and verified by measurement results.

60-GHz Integrated Transmitter Development in 90-nm CMOS

In this study, two 60-GHz single-chip CMOS transmitters have been fully integrated in a standard 90-nm CMOS process, focusing on low-power and high-performance applications, respectively. The low-power transmitter lineup consists of a push-push voltage-controlled oscillator (VCO), a single-gate up-conversion mixer, and a low-power three-stage power amplifier. The high-performance transmitter lineup consists of a cross-coupled VCO, a double-balanced Gilbert-cell up-conversion mixer with an on-chip Marchand balun, and a high linearity three-stage power amplifier. Measured performances of both the VCOs exhibit a wide tuning range of more than 2 GHz. The low-power single-gate up-converter provides a conversion loss of 8.4 dB, as compared to 4-dB conversion loss for the double-balanced Gilbert-cell up-converter, with 28-mW lower power consumption. The high-performance transmitter provides a total gain of more than 12 dB, with the power amplifier achieving 17-dB small-signal gain, and delivers +8.6-dBm saturated output power at 63 GHz for total power consumption of 112 mW. The low-power transmitter lineup provides a gain of 8.4 dB with a 5.7-dBm saturated output power for a 30% lower power consumption, and hence, presents an excellent tradeoff in terms of overall gain, output power, and total power consumption. After evaluating performances of these two lineups, an optimum lineup has been chosen where a double-balanced Gilbert-cell up-converter and Marchand balun of high-performance lineup are replaced by a dual-gate up-converter. This optimum transmitter front-end lineup delivers same performance as high-performance transmitter lineup, but with 10% reduced size and reduced total power consumption of 94 mW. All the designs have been optimized for robustness against process variation and temperature, and verified by measurement results. Transmitters achieve a 3-dB RF bandwidth exceeding 8 GHz (57-65 GHz).

A novel electromagnetic bandgap metal plate for parallel plate mode suppression in shielded structures

A novel type of metal plate structure incorporated with electromagnetic bandgap holes for use as metal shields with the capability of suppressing the propagation of unwanted parallel plate mode has been proposed. The holes can be of any shape and the periods of those holes should be selected to half the guided wavelength of the parallel plate mode at a desired center frequency of suppression. To show the validity of the proposal, inert electromagnetic wave simulation, results of a shielded microstrip structure designed for application in the 76 GHz frequency band are demonstrated. Experiments are performed with a prototype designed in the 10 GHz frequency band and parallel plate mode suppression is verified successfully with the excellent agreement between experimental and simulation results.

60GHz CMOS power amplifier with 20-dB-gain and 12dBm Psat

A 60 GHz power amplifier with 20dB small signal gain is designed and fabricated using standard 1P7M 90nm CMOS process technology. An excellent correlation between the simulation and measurement is demonstrated. The 3-dB bandwidth exceeding 57 to 65 GHz is achieved. This power amplifier delivers +8.2dBm output P1dB with a linear gain of 20dB and a saturated output power of +12.0dBm with maximum PAE of 9.0% at 1.2V operation. When it is operated at 1.5V it achieves 22dB small signal gain, 10.0dBm output P1dB and 12.4dBm saturated output power. This is the highest gain along with high output power and high max PAE CMOS power amplifier operating in the 60 GHz unlicensed band reported till date. A temperature dependent scalable CMOS device model has been developed for the first time, implementing in the design of the power amplifier and the measured output power characteristics of this 60GHz CMOS power amplifier shows very stable operation over the entire temperature range between −10°C and +80°C.

17-dB-gain CMOS power amplifier at 60GHz

A 60 GHz power amplifier with 17dB small signal gain is designed and measured using standard 90nm CMOS process technology. Simulation predicted accurate performances. The 3-dB bandwidth exceeding 57 to 65 GHz is achieved. This power amplifier delivers +5.1dBm output P1dB with a maximum gain of 17dB at 61 GHz for 54mW total DC consumption, achieving 5.8% PAE and a saturated output power of +8.4dBm at 60GHz. This is the highest gain CMOS power amplifier operating in the 60 GHz unlicensed band reported till date. The first temperature dependent output power characteristics of 60GHz CMOS power amplifier shows very stable operation over the entire temperature range between 0°C and +80°C.

60-GHz LNA using a Hybrid Transmission Line and Conductive Path to Ground Technique in Silicon

A monolithic 60 GHz low-noise amplifier (LNA) using a passive noise suppression technique and an enhanced hybrid transmission line structure, fabricated in a 0.12 mum SiGe BiCMOS process is presented. This design provides the entire circuit with a conductive path to ground the P-substrate. Near active device regions, noise injection and crosstalk paths are shunted to ground. Measurements of the single-stage LNA show peak performance at 59 GHz exhibiting a gain of 14.5 dB, a NF of 4.1 dB, a + 1.5 dBm output compression point, while consuming 4.5 mA from a 1.8 v supply. Across the entire V-band (57 - 64 GHz), the LNA provides a minimum gain of 12 dB with an average noise figure of 5 dB. This LNA has the highest known figure of merit reported for a 60 GHz application.

60GHz CMOS/PCB co-design and phased array technology

In this paper, we present a highly integrated 60 GHz CMOS/PCB single-chip digital phased array solution, embedded in QFN package. This represents a unique opportunity to develop low power 60GHz multi-gigabit radio at a similar cost structure as a Bleutooth® radio, addressing the needs of a multitude of bandwidth hungry wireless multimedia applications such as high definition streaming and massive side-loading. The convergence of 60GHz CMOS digital radio, phased array technology, low power multi-gigabit mixed-signal processing low cost filter, phased array antenna embedded in standard package is discussed. In addition, uncompressed HDMI video streaming is demonstrated for the first time, using a standard battery (AAA) operated compact 60GHz CMOS/PCB QFN based module. These solutions offer the lowest energy per bit transmitted wirelessly at multi-gigabit rate, reported till date, to meet the very stringent low-power specifications for battery operated consumer electronic portable devices.

Development of CMOS Based Circuits for 60GHz WPAN applications

Recent interest in the 60 GHz band for high data rate short range wireless links has led to the significant progress in the development of integrated circuits for RF front-ends. CMOS process technology is being widely discussed for low-cost, low power mm-wave radio systems applications. In this paper we discuss various CMOS based circuits which have been developed considering carefully all the aspects such as device characterizations, the circuit topology, the circuit layouts, integration on a lost packaging for high volume fabrication lowering the cost and opening huge commercial opportunities of millimeter wave technology in the consumer electronic market place in a fairly near future.