Padmanava Sen

A 90nm CMOS 60GHz Radio

CMOS-based circuits operating at mm-wave frequencies have emerged in the past few years. This paper discusses the integration of a 60GHz CMOS single-chip transmitter and a single- chip receiver using a standard 90nm CMOS technology demonstrating a reliable solution for 60GHz single-chip radio. Proper transistor layout, complete and accurate modeling and optimized parasitic extraction method enabled the robust design of the wideband super-heterodyne architecture to support the entire 57- to-66GHz band. The analog radio front-end is controlled by a serial digital interface and has been co-designed and integrated together with a high-speed digital signal processor including analog-to-digital conversion, high speed PHY signal processing such as frequency-offset compensation, phase tracking, FIR and DFE, to support both advanced OFDM and SCBT modulation scheme. The resulting single-chip solution enables data throughputs exceeding 7Gb/s (QPSK) and 15Gb/s (16QAM) for a total DC power budget of below 200mW in TDD operation. In combination with a low-cost FR4-based packaging technology, it provides a high-performance cost-effective solution for a wide range of high volume consumer electronic applications.

Reconfigurable RFICs in Si-based technologies for a compact intelligent RF front-end

This paper presents reconfigurable RF integrated circuits (ICs) for a compact implementation of an intelligent RF front-end for multiband and multistandard applications. Reconfigurability has been addressed at each level starting from the basic elements to the RF blocks and the overall front-end architecture. An active resistor tunable from 400 to 1600 /spl Omega/ up to 10 GHz has been designed and an equivalent model has been extracted. A fully tunable active inductor using a tunable feedback resistor has been proposed that provides inductances between 0.1-15 nH with Q>50 in the C-band. To demonstrate reconfigurability at the block level, voltage-controlled oscillators with very wide tuning ranges have been implemented in the C-band using the proposed active inductor, as well as using a switched-spiral resonator with capacitive tuning. The ICs have been implemented using 0.18-/spl mu/m Si-CMOS and 0.18-/spl mu/m SiGe-BiCMOS technologies.

60 GHz single-chip 90nm CMOS radio with integrated signal processor

A 60GHz single-chip CMOS radio has been fully integrated using standard 90nm CMOS process technology. The digitally controlled wideband super-heterodyne architecture combined with a high-speed digital signal processor has been designed to support the whole 57 to 66 GHz bandwidth available, and enable data throughput exceeding 7Gbps QPSK and 15Gbps 16QAM for a total DC power budget below 200mW. The receiver chain provides a total gain of nearly 50dB for a total noise figure below 9dB while the power amplifier delivers +8.4dBm saturated output power at 60GHz. The single-chip radio is digitally controlled via a standard SPI, and scalable to a phased array architecture. This is the highest level of integration for a 60GHz single-chip transceiver reported till date. The design has been optimized for robustness against process variation and temperature, and verified by measurement results.

60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity

In this paper, we present four examples of highly integrated 60 GHz single-chip CMOS 90 nm digital radios and phased array solutions. These solutions include for the first time digital-to-analog/analog-to-digital conversion and embedded multi-gigabit mixed signal modem requiring no external processing. This convergence of 60 GHz CMOS digital radio, low power multi-gigabit mixed-signal processing and digital signal processing on a single chip offers the lowest energy per bit transmitted wirelessly at multi-gigabit rate to meet the very stringent low-power specifications for battery operated consumer electronic portable devices. Layout and temperature dependent 60 GHz CMOS 90 nm model development and critical high performance analog and mixed building blocks are presented as fundamental enablers for single chip integration. The designs have been optimized for robustness against process variation and temperature, and verified by measurement results.

60-GHz Integrated Transmitter Development in 90-nm CMOS

In this study, two 60-GHz single-chip CMOS transmitters have been fully integrated in a standard 90-nm CMOS process, focusing on low-power and high-performance applications, respectively. The low-power transmitter lineup consists of a push-push voltage-controlled oscillator (VCO), a single-gate up-conversion mixer, and a low-power three-stage power amplifier. The high-performance transmitter lineup consists of a cross-coupled VCO, a double-balanced Gilbert-cell up-conversion mixer with an on-chip Marchand balun, and a high linearity three-stage power amplifier. Measured performances of both the VCOs exhibit a wide tuning range of more than 2 GHz. The low-power single-gate up-converter provides a conversion loss of 8.4 dB, as compared to 4-dB conversion loss for the double-balanced Gilbert-cell up-converter, with 28-mW lower power consumption. The high-performance transmitter provides a total gain of more than 12 dB, with the power amplifier achieving 17-dB small-signal gain, and delivers +8.6-dBm saturated output power at 63 GHz for total power consumption of 112 mW. The low-power transmitter lineup provides a gain of 8.4 dB with a 5.7-dBm saturated output power for a 30% lower power consumption, and hence, presents an excellent tradeoff in terms of overall gain, output power, and total power consumption. After evaluating performances of these two lineups, an optimum lineup has been chosen where a double-balanced Gilbert-cell up-converter and Marchand balun of high-performance lineup are replaced by a dual-gate up-converter. This optimum transmitter front-end lineup delivers same performance as high-performance transmitter lineup, but with 10% reduced size and reduced total power consumption of 94 mW. All the designs have been optimized for robustness against process variation and temperature, and verified by measurement results. Transmitters achieve a 3-dB RF bandwidth exceeding 8 GHz (57-65 GHz).

60GHz CMOS power amplifier with 20-dB-gain and 12dBm Psat

A 60 GHz power amplifier with 20dB small signal gain is designed and fabricated using standard 1P7M 90nm CMOS process technology. An excellent correlation between the simulation and measurement is demonstrated. The 3-dB bandwidth exceeding 57 to 65 GHz is achieved. This power amplifier delivers +8.2dBm output P1dB with a linear gain of 20dB and a saturated output power of +12.0dBm with maximum PAE of 9.0% at 1.2V operation. When it is operated at 1.5V it achieves 22dB small signal gain, 10.0dBm output P1dB and 12.4dBm saturated output power. This is the highest gain along with high output power and high max PAE CMOS power amplifier operating in the 60 GHz unlicensed band reported till date. A temperature dependent scalable CMOS device model has been developed for the first time, implementing in the design of the power amplifier and the measured output power characteristics of this 60GHz CMOS power amplifier shows very stable operation over the entire temperature range between −10°C and +80°C.

17-dB-gain CMOS power amplifier at 60GHz

A 60 GHz power amplifier with 17dB small signal gain is designed and measured using standard 90nm CMOS process technology. Simulation predicted accurate performances. The 3-dB bandwidth exceeding 57 to 65 GHz is achieved. This power amplifier delivers +5.1dBm output P1dB with a maximum gain of 17dB at 61 GHz for 54mW total DC consumption, achieving 5.8% PAE and a saturated output power of +8.4dBm at 60GHz. This is the highest gain CMOS power amplifier operating in the 60 GHz unlicensed band reported till date. The first temperature dependent output power characteristics of 60GHz CMOS power amplifier shows very stable operation over the entire temperature range between 0°C and +80°C.

Reconfigurable RFICs for frequency-agile VCOs in Si-based technology for multi-standard applications

This paper presents novel reconfigurable RFICs for intelligent radio applications. It includes a new fully tunable active inductor (TAI) along with frequency-agile VCOs. The ICs are implemented on both 0.18 /spl mu/m Si-CMOS and 0.18 /spl mu/m SiGe-BiCMOS technologies. The novelty of the TAI lies in the use of a tunable active feedback resistor that results in inductances tunable from 0.1 nH to 15 nH with Q < 50 in C-band. Very wideband reconfigurable VCOs have been implemented using the proposed active inductor, and also with a switched-spiral topology. The VCO tuning ranges are as high as 4 GHz in the C-band. Analysis of the results, taking into account the technologies as well as the circuit topologies, is also presented.

60GHz CMOS/PCB co-design and phased array technology

In this paper, we present a highly integrated 60 GHz CMOS/PCB single-chip digital phased array solution, embedded in QFN package. This represents a unique opportunity to develop low power 60GHz multi-gigabit radio at a similar cost structure as a Bleutooth® radio, addressing the needs of a multitude of bandwidth hungry wireless multimedia applications such as high definition streaming and massive side-loading. The convergence of 60GHz CMOS digital radio, phased array technology, low power multi-gigabit mixed-signal processing low cost filter, phased array antenna embedded in standard package is discussed. In addition, uncompressed HDMI video streaming is demonstrated for the first time, using a standard battery (AAA) operated compact 60GHz CMOS/PCB QFN based module. These solutions offer the lowest energy per bit transmitted wirelessly at multi-gigabit rate, reported till date, to meet the very stringent low-power specifications for battery operated consumer electronic portable devices.

Linear RF CMOS power amplifier with improved efficiency and linearity in wide power levels

We demonstrate for the first time that both linearity and efficiency can be optimized for CMOS power amplifiers in the gigahertz range. A technique using large and small transistors in parallel at the output stage for efficiency and linearity enhancement is proposed. A small transistor is used for low power amplification where a larger transistor is turned off to reduce DC power consumption and increase efficiency in the back-off region. The method of improving the linearity of FET amplifiers by offsetting the gate bias to cancel the nonlinearity products is implemented in combination with the efficiency enhancement. For the first time, both techniques are incorporated in the design of a 1.9 GHz CMOS power amplifier that achieves a power-added efficiency (PAE) of 22% at 23-dBm output power. PAE at 6-dB power back-off is measured to be 15%, which exhibits a factor of 2 improvement from the normal class-AB design. Also, third-order intermodulation is improved by approximately 8 dB in the high-power mode of operation when the linearity improvement technique is applied. In addition, this technique does not use transmission line or additional circuits, thus making it ideal for integrated circuit RF power amplifier design.