Seung-Chul Song

Accurate projection of V ccmin by modeling “dual slope” in FinFET based SRAM, and impact of long term reliability on end of life V ccmin

Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin is required to meet the high target yield because the SRAM yield according to Vcc scaling shows “dual slope”. In this paper, the root causes of “dual slope” are analyzed. Both side effect of SRAM bitcell on the yield is also considered to accurately project Vccmin, which results in 40mV increase of Vccmin to meet 99% target yield for 32nm HK/MG planar 1M SRAM. The “dual slope” effect on the yield is compared for 32nm HK/MG planar and FinFET 32M SRAMs with high (HD) and low doping (LD). Under the “dual slope” effect, the channel length adjustment method for pass gate transistor is proposed to reduce Vccmin of FinFET SRAM. When the number of finis is 1∶2∶2(=PU∶PG∶PD), HD and LD 32M FinFET SRAMs improve Vccmin by 370mV and 500mV, respectively, compared to 32M planar counterparts using the proposed the channel length adjustment method. Effect of NBTI and PBTI on Vccmin is also investigated. BTI degradation is greatly dependent on HK thickness and surface plane orientation of FinFET. End of Life (EOL) Vccmin optimization therefore requires careful selection of HK thickness and surface orientation.

Holistic technology optimization and key enablers for 7nm mobile SoC

We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (R_wire) multiplied by logic gate input pin cap (C_pin), R_wire×C_pin, is identified as a major limiter of performance and power at N7. Reducing C_pin is crucial to mitigate abruptly rising BEOL R_wire effect. Depopulation of fin is one of most effective methods to reduce C_pin, and scale the logic gate area. Air Spacer (AS) on transistor sidewall is proposed to further reduce C_pin, whose benefit is enhanced by reduction of other C_pin components. Careful choice of routing metal stack ameliorates adverse effect of R_wire. Wrap-Around-Contact (WAC) over Source and Drain of scaled fin pitch (P_fin) is needed to reduce transistor resistance (R_tr). Fin depopulation with other cost effective process innovations significantly improve Power-Performance-Area-Cost (PPAC) of N7, enabling continued scaling of mobile System on a Chip.

Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) architectures, are introduced having higher current drivability and lower parasitic capacitance than conventional NW or NanoSlab devices. The standard cell sizing options, including a 1-fin-per-device version and a 2-fin-per-device design, are systematically evaluated. Each device flavor has multiple vertical stacks when wire-like or slab-like structure is used. Comprehensive transistor and logic cell studies demonstrate that the novel NR is the optimal structure for N5 and beyond.

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes

We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to authors previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization

We present, for the first time, a holistic data-path driven transistor-interconnect co-optimization method, which systematically isolates the logic-gate and interconnect-wire dominated data-paths in block-level delay-bins (i.e., sub-binning of delay based bins) to significantly improve accuracy of static and dynamic power estimation. It captures the critical interdependence of transistor architecture (FEOL) including local interconnect, and BEOL metal stack optimization to achieve holistic 10nm (N10) technology optimization at target speeds. Using the proposed method, we drive >2.5x Performance/Watt (PpW) improvement for N10 FinFET SOC design over 14nm (N14). Even with ∼3x higher wire resistance of min metal width, the PpW @target-speed for N10 improves >2.5x over N14 with proper design of metal/via stack, transistor Vt and fin-profile as well as standard-cell architecture. Reducing active fin-count and routing distance between standard-cells is a critical design knob for N10 mobile SOC enablement. The proposed methodology enables smartphone-usage (days-of-use) based technology optimization, driving longer battery-life in mobile SOCs, keeping process cost and complexity at minimum.

Electrostatics and performance benchmarking using all types of III–V multi-gate FinFETs for sub 7nm technology node logic application

In this paper, we conducted the sub 7nm technology benchmarking for logic application using performance comparison between III-V multi-gate(double, tri, gate-all-around) nMOSFET and Si nFinFET. The benchmarking was executed based on the physical parameters extracted from Virtual-Source(VS) modeling and well-calibrated TCAD simulation. Especially by quantitatively investigating fin width(Wfin) and interface trap(Dit) effects on electrostatic of III-V multi-gate(MG) nMOSFET which is critical to device scaling, we proposed a device design strategy for sub 7nm technology node.

Technology-design-manufacturing co-optimization for advanced mobile SoCs

How to maintain the Moore’s Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

PPAC scaling enablement for 5nm mobile SoC technology

We present a 5nm logic technology scaling step-up holistic approach for 5-track standard cell design employing electrically gate-all-around nanowire architecture (EGAA NW) with much reduced parasitic capacitance and increased effective width for better short channel control and stronger drive. We suggest SiGe P-channel by Ge Condensation for intrinsic mobility improvement and substrate strain, conformal wraparound contact (CWAC) to reduce contact resistance with minimum parasitic capacitance penalty, metal gate (MG) stressor to improve N-channel mobility, EUV single exposure metal patterning with improved tip-to-tip patterning technique for maximum mask count reduction, and Al metallization to reduce metal & via resistances, however still requiring a validation of the proposed electromigration (EM) risk mitigation. We show that finFET can still be extended to 5nm technology to meet Power-Performance-Area-Cost (PPAC) targets. EGAA NW could enable further 50mV less supply voltage to significantly improve 5nm PPAC scaling.

10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling

The industrys first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.