James Walter Blatchford

Capacitance Analysis of Highly Leaky

Characterization of metal-insulator-metal (MIM) capacitors with a scaled dielectric is a challenge using conventional capacitance-voltage (C-V) measurements due to a high leakage current. In this letter, a method to analyze MIM capacitance that is more immune to the leakage current problem has been successfully demonstrated using time domain reflectometry (TDR). The TDR method can be applied to Al2O3 MIM capacitors with a capacitance density up to ~ 11.1 fF/μm2, for which an impedance analyzer has failed to measure capacitance at 1 MHz. Differences in the voltage coefficient of capacitance and dielectric constant (k) were also investigated.

\hbox{Al}_{2} \hbox{O}_{3}

Temperature dependent current-voltage measurements show that the addition of only 10% Pt to NiSi causes an increase of Schottky barrier height (SBH) from 0.65 eV for NiSi to 0.78 eV for the 10% Pt alloy. Internal photoemission measurements resolve two SBHs in all alloyed samples with ≥5% Pt incorporation corresponding to NiSi and PtSi (∼0.68 eV and ∼0.80 eV), proving that each contributes independently to junction current. High angle annular dark field imaging with scanning transmission electron microscopy confirms Pt segregation to the Ni(Pt)Si/Si interface. The resulting increased SBH may therefore be detrimental to contact resistivity in future technology nodes.

MIM Capacitors Using Time Domain Reflectometry

With the delay of a next-node lithography solution, lithographers are required to evaluate double patterning techniques such as double pattern/double etch (DP/DE) to meet scaling targets for the 22nm logic node. The tightest design rule level to pattern has traditionally been the first metal level. For this node, target minimum pitches are below 32 nm half pitch in order to meet cell area requirements. In this paper, we explore implications of the DP/DE approach when applied to complex 2D metal patterns. In addition to evaluating stitching rules for line ends, we move into complicated patterning structures such as landing pads neighboring metal runners and arrays of dense landing pads. These feature types are critical for area scaling; however, when these structures are patterned in a DP/DE scheme, the minimum area of the features needed for each pattern layer can be quite small. In this work, we explore minimum area rules for stitching together patterns as function of overlap with first pattern, minimum area and proximity to unrelated trench features on the same pattern. These results are shown thru simulation and on the wafer scale using a DP/DE approach which uses current 28 nm node imaging techniques.

PtSi dominated Schottky barrier heights of Ni(Pt)Si contacts due to Pt segregation

Contact resistance (Rc) contributes over 65% of the total source to drain series resistance in <; 32 nm CMOS technologies. In this work, reduction of Rc is achieved by lowering the SBH through the incorporation of new materials into NiPtSi. The impact of implanted elemental species as well as alloyed low work function metals is discussed. As diffusion and subsequent interface composition is highly dependent on the incorporated material, these NiPtSi junctions with complex composition are often inhomogeneous, making SBH extraction a less trivial task. Advanced analysis for extracting the true SBH of these junctions will also be presented.