Deepak Kumar Nayak

Enhancement of CMOS performance by process-induced stress

A detailed analysis of the process-induced stress during a standard CMOS manufacturing is presented. Dependence of transistor performance on layout is attributed to the combination of stress induced by shallow trench isolation and source/drain (S/D) silicide. Based on the layout sensitivity, the effect of an individual stress component on NMOS and PMOS is identified. The optimization of transistor layout is proposed to improve the CMOS performance.

Oxide reliability of drain engineered I/O NMOS from hot carrier injection

The impact of hot carrier stress on the breakdown properties of I/O NMOS gate oxide is reported. I/O NMOS devices with drain structures using standard LDD with pocket (S-LDD) and graded LDD without pocket (G-LDD) are used. Time-dependent (TDDB) and voltage-ramp (VRDB) dielectric breakdown tests are performed for devices with and without hot-carrier-injection. It is demonstrated that both I/O structures show similar oxide integrity after hot carrier injection (HCI) when the Idsat degradation is small (<5%), but show significantly different oxide lifetimes when the Idsat degradation is high (>5%). At 10% I/sub dsat/ degradation, the oxide lifetime for the G-LDD structure is reduced by about a factor of 10 compared to that of the S-LDD structure. The correlation between oxide integrity and leakage current indicates that the oxide charge introduced by HCI stress is the reason for oxide degradation. This work clearly demonstrates that the effect of hot carrier induced oxide damage must be included when predicting the oxide lifetimes of advanced I/O NMOS devices.

Mechanism and Modeling of PMOS NBTI Degradation with Drain Bias

A new mechanism for PMOS NBTI (negative biased temperature instability) with drain bias is presented. The turnaround behavior of device degradation is explained. While drain bias reduces gate oxide voltage and causes less NBTI, the channel-hot-hole enhances the NBTI degradation. For the first time, a semi-empirical model is proposed that fits well with the experimental data, including various parameters, such as temperature, voltage, channel length, and drive current.

Improved

Conventional CV/I methodology is shown to be inadequate in projecting circuit performance of advanced technologies. The calculation can result in over 100% error on performance estimates compared to the silicon data. In this brief, we present an improved CV/I model that predicts performance within 3% error against ring oscillator delays over different technology nodes. The model is highly scalable and can be used as figure of merit for future technology performance assessment.

CV/I

Strain-Si field-programmable gate arrays (FPGA) is fabricated by using ultimate spacer process (USP) with a single capping stress liner. An overall 15% speed enhancement without compromising yield was obtained. The product reliability assessment, including HTOL, TCT, ESD (CDM and HBM) and latch-up, was performed simultaneously on USP and control parts. They show comparable product reliability and both pass product specs. Wafer level device reliability was also studied for NBTI, HCI and oxide TDDB. Wafer level NBTI is well correlated with product level HTOL degradation. It is confirmed that USP technology improves product performance significantly, and the product reliability is comparable to that of baseline technology