Daniel Gitlin

Oxide reliability of drain engineered I/O NMOS from hot carrier injection

The impact of hot carrier stress on the breakdown properties of I/O NMOS gate oxide is reported. I/O NMOS devices with drain structures using standard LDD with pocket (S-LDD) and graded LDD without pocket (G-LDD) are used. Time-dependent (TDDB) and voltage-ramp (VRDB) dielectric breakdown tests are performed for devices with and without hot-carrier-injection. It is demonstrated that both I/O structures show similar oxide integrity after hot carrier injection (HCI) when the Idsat degradation is small (<5%), but show significantly different oxide lifetimes when the Idsat degradation is high (>5%). At 10% I/sub dsat/ degradation, the oxide lifetime for the G-LDD structure is reduced by about a factor of 10 compared to that of the S-LDD structure. The correlation between oxide integrity and leakage current indicates that the oxide charge introduced by HCI stress is the reason for oxide degradation. This work clearly demonstrates that the effect of hot carrier induced oxide damage must be included when predicting the oxide lifetimes of advanced I/O NMOS devices.

Mechanism and Modeling of PMOS NBTI Degradation with Drain Bias

A new mechanism for PMOS NBTI (negative biased temperature instability) with drain bias is presented. The turnaround behavior of device degradation is explained. While drain bias reduces gate oxide voltage and causes less NBTI, the channel-hot-hole enhances the NBTI degradation. For the first time, a semi-empirical model is proposed that fits well with the experimental data, including various parameters, such as temperature, voltage, channel length, and drive current.

The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance

The impact of plasma-induced damage on the speed performance of a field programmable gate array (FPGA) is presented. It was found that FPGA speed degradation induced by product reliability burn-in was directly related to a large negative threshold voltage (V/sub t/) shift of the surface channel PMOS induced by negative bias temperature (BT) stress. Such negative bias temperature instability (NBTI) in the PMOS was shown to be related to specific back-end plasma processing steps. An overall reduction in NBTI of the PMOSFET was observed when certain plasma processing steps were eliminated which in turn resulted in the reduction of FPGA performance degradation.

Graded tunnelling barrier and oxygen concentration in thermally grown ultrathin SiOx gate oxide

Barrier parameters of a thermally grown SiOx gate oxide are derived by relating the SIMS oxygen concentration profile to the barrier height. Even in the simple analytical form such a graded barrier model agrees with the tunnelling current and its voltage dependence in both directions. Asymmetrical tunnelling I?Vs in the symmetrical n+Si?SiOx?n+Si structure are due to both graded barrier and penetration of carriers into the gate oxide at the SiOx?Si substrate interface.

Current through SiO2 gate oxide and its low frequency fluctuations: Trapping on charged dangling bonds with negative Hubbard U

An estimate of Hubbard U supports instability of neutral one-electron Si dangling bonds in SiO2 and the formation of charged two-electron and two-hole negative U centers through the reaction Si•+Si•→Si++Si−••. The trapping on these negative U centers creates and annihilates “dents” in the thin barrier for electron and hole tunneling through the gate oxide. Such dents are visible as gate current low frequency fluctuations (1∕f noise). The longer trapping time of holes causes irreversible Si−••→Si+ conversion, which leads to stress-induced leakage current and accumulation of positive charge in the oxide under voltage stress.

Understanding degradation and breakdown of SiO2 gate dielectric with “negative Hubbard U” dangling bonds

Degradation and time dependent breakdown of SiO2 gate oxides are discussed based on the Anderson–Mott theory of amorphous solids with dangling bonds as diamagnetic “negative Hubbard U” centers. Negative-U dangling bonds in the oxide are either positive D+ centers or two-electron negative D− centers. Due to a large difference in mobility between electrons and holes, hopping current in SiO2 is mainly electron current on D+ centers. Degradation of isolation properties and time dependent breakdown of SiO2 gate oxide under voltage stress are due to the conversion of D− into D+ centers caused by the hole-hopping current in SiO2. The reaction of conversion is stress polarity dependent. Thermal conductivity of Si is approximately 100 times higher than thermal conductivity of SiO2. Heat dissipation and accumulation of D+ centers inside the oxide are important in understanding the time dependent breakdown of the oxide.

Dangling bonds with “negative Hubbard U ”: Physical model for degradation of SiO2 gate dielectric under voltage stress

A model proposed to explain the phenomenon of current increase and its fluctuation under voltage stress in a SiO2 gate dielectric is based on the amorphous nature and presence of dangling bonds in SiO2. Dangling bonds D0 are thought to be negative-U centers, where their neutral state is unstable and therefore a spontaneous reaction of charge disproportionation take place: D0+D0→D++D−. As a result, a SiO2 amorphous network has diamagnetic positive D+ and negative D− centers. Due to a large difference in mobility between electrons and holes, hopping current in SiO2 is mainly electron current on D+ centers. Current increase and fluctuation under a voltage stress is due a conversion of D− into D+ centers by the hole component of current through SiO2 gate dielectric. This conversion is an irreversible process accelerated by temperature and electric field.

Improved

Conventional CV/I methodology is shown to be inadequate in projecting circuit performance of advanced technologies. The calculation can result in over 100% error on performance estimates compared to the silicon data. In this brief, we present an improved CV/I model that predicts performance within 3% error against ring oscillator delays over different technology nodes. The model is highly scalable and can be used as figure of merit for future technology performance assessment.

CV/I

Strain-Si field-programmable gate arrays (FPGA) is fabricated by using ultimate spacer process (USP) with a single capping stress liner. An overall 15% speed enhancement without compromising yield was obtained. The product reliability assessment, including HTOL, TCT, ESD (CDM and HBM) and latch-up, was performed simultaneously on USP and control parts. They show comparable product reliability and both pass product specs. Wafer level device reliability was also studied for NBTI, HCI and oxide TDDB. Wafer level NBTI is well correlated with product level HTOL degradation. It is confirmed that USP technology improves product performance significantly, and the product reliability is comparable to that of baseline technology