Jae-Gyung Ahn

Product-Level Reliability Estimator with advanced CMOS technology

A Product-Level Reliability Estimator (PLRE), which calculates failure rate of a chip as a function of use conditions, has been developed for the first time. Major wafer-level failure mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) and Electro Migration (EM) are included. By applying PLRE to the product with advanced CMOS technology, contributions from each block and each failure mechanism were quantitatively identified. It was shown that, at the target time-to-failure (TTF), gate dielectric (GD) TDDB takes the biggest portion of the failure rate, but the first failure comes with EM.

Product-level reliability estimator with budget-based reliability management in 16nm technology

Product-level Reliability Estimator (PLRE) has been built for 20nm technology product. With PLRE, users can estimate failure rate of the chip with various use conditions. EDA tools are used to estimate each blocks reliability budget, in terms of effective area for TDDB and effective number for EM which are to be used in building PLRE. Budget-based reliability check procedure was explained, which let designers have more room for reliability to get better circuit performance. Results of PLRE show that EM and MOL TDDB can be an actual risk in specific use condition.

Budget-based reliability management to handle impact of thermal issues in 16nm technology

We handle the thermal impact on FEOL and BEOL reliability by using new aging simulation flow and EM checking flow which is considering thermal coupling effects from both FinFET SHE and metal wire JHE. We demonstrated how the budget-based reliability checking flow works with thermal issues and showed that it checks product risk more rigorously and less conservatively. It results in providing more freedom to circuit designers by allowing higher temperature increase and thus helping them to achieve high performance circuit.

Voltage Ramp Stress Test to determine TDDB performance in SRAM vehicle

We applied Voltage Ramp Stress Test (VRST) to an SRAM test vehicle and compared the obtained Vfail distribution with theoretical predictions from various TDDB failure criteria. Measured Vfail results are matched with the prediction from TDDB failure criterion of Ig/Ig0=1000 or more. We developed a numerical method to predict effective Igate with TDDB stress. It was applied to VRST condition and shows good agreement with measured data.

Systematic Approach to Design High Power FPGA Package for Current-Carrying Capability

This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution and to calculate accumulated failure rates from an entire substrate including BGA ball, micro-via and plated through hole. The approach reported here allows lifetime calculation from the progressive failure of individual BGA over the different time span. In the end, we apply the methodology to a 200A high power design achieved with the most efficient ball count that meets lifetime specification.

High power FPGA package design to maximize current-carrying capability

The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design for optimal current distribution directly to failure rate as a result of electro-migration (EM) in stated lifetime. Secondly, a specific design case is analyzed with the new method to show how BGA pin pattern can impact maximal current carrying capability.

Design-in reliability for over drive applications in advanced technology

We present the FEOL reliability checking flow in advanced technology especially with over drive applications. We check gate bias values obtained from SPICE transient simulation against the maximum allowed value, Vg_max, to make sure robust gate dielectric reliability. We set up HSPICE MOSRA simulation procedure to let designers check the impact of BTI and HCI to each MOSFET device and the circuit performance at End-of-Lifetime (EOL). From HCI degradation analysis from HSPICE MOSRA, we obtained a good correlation between HCI damage and slew rate and conditions in which HCI degradation is negligible. We discuss on the selection of the stress conditions and monitor conditions to be checked. We applied HSPICE MOSRA to several over drive applications and were able to successfully justify them with careful modeling for HCI and NCHC in addition to BTI.