Ming-Yin Hao

Oxide reliability of drain engineered I/O NMOS from hot carrier injection

The impact of hot carrier stress on the breakdown properties of I/O NMOS gate oxide is reported. I/O NMOS devices with drain structures using standard LDD with pocket (S-LDD) and graded LDD without pocket (G-LDD) are used. Time-dependent (TDDB) and voltage-ramp (VRDB) dielectric breakdown tests are performed for devices with and without hot-carrier-injection. It is demonstrated that both I/O structures show similar oxide integrity after hot carrier injection (HCI) when the Idsat degradation is small (<5%), but show significantly different oxide lifetimes when the Idsat degradation is high (>5%). At 10% I/sub dsat/ degradation, the oxide lifetime for the G-LDD structure is reduced by about a factor of 10 compared to that of the S-LDD structure. The correlation between oxide integrity and leakage current indicates that the oxide charge introduced by HCI stress is the reason for oxide degradation. This work clearly demonstrates that the effect of hot carrier induced oxide damage must be included when predicting the oxide lifetimes of advanced I/O NMOS devices.

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L/sub eff/ of 0.19 /spl mu/m, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA//spl mu/m at 2.9 V have been achieved.

Effect of local interconnect etch-stop layer on channel hot-electron degradation

Routine use of an etch-stop layer during semiconductor processing favors circuit density and performance through the use of local interconnect and similar damascene processes, and also allows the use of manufacturable etch recipes. Previous studies have demonstrated that post transistor definition, topside passivation and deposition techniques can significantly impact device degradation characteristics. This work further investigates the choice of local interconnect etch-stop layer and its effect on channel hot-electron degradation. A reduction in channel hot-electron degradation is demonstrated through the use of N2O anneal gate oxide, and using experimental data a possible degradation mechanism, caused by the presence of the etch-stop layer, is identified. A brief review of the compatibility of etch-stop layers with high performance 0.3 micrometer CMOS devices is presented through interface state and hot-electron stress measurements.

Device performance and optimization for 5th- and 6th-generation microprocessors

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.

Impact of boron penetration at the p/sup +/-poly/gate-oxide interface on the device reliability of deep submicron CMOS logic technology

Impact of boron penetration at the p/sup +/-poly/gate-oxide interface is investigated. It is shown that the onset of boron penetration at this interface can not be detected by conventional threshold or flatband voltage shifts of p-channel devices, but it results in significantly lower Q/sub BD/ and Vt instability. Constant current stress in inversion has been found to be most sensitive technique to monitor the onset of boron at the p/sup +/-poly/gate-oxide interface.