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Dive into the research topics where Deepak Nayak is active.

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Featured researches published by Deepak Nayak.


ieee soi 3d subthreshold microelectronics technology unified conference | 2015

Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs

Deepak Nayak; Srinivasa Banna; Sandeep Kumar Samal; Sung Kyu Lim

Power, performance, area, and cost analysis of TSV, mini-TSV, and monolithic 3D ICs is presented. Power savings for TSV, mini-TSV, and monolithic 3D ICs are 21%, 25%, and 37%, respectively, compared to that of a 2D IC. It is shown that monolithic 3D can deliver one node PPC benefit, whereas TSV 3D or mini-TSV 3D can only achieve a half node PPC advantage.


ieee computer society annual symposium on vlsi | 2016

On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs

Jiajun Shi; Deepak Nayak; Motoi Ichihashi; Srinivasa Banna; Csaba Andras Moritz

Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology node scaling. Transistor-level (TR-L) monolithic 3D IC is the most advanced and fine-grained M3D IC technology. In this paper, for the first time, the detailed design as well as benefits and challenges of a silicon validated 14nm Finfet process design kit (PDK) based TR-L M3D IC technology is explored. TR-L M3D standard cell layout is achieved based on 14nm Finfet design rules and feature sizes. A semi-customized RC extraction methodology is performed for accurate 3D cell RC extraction. After extensive simulation, TR-L M3D cell power, delay and area are evaluated and compared with equivalent 2D cells in the same technology node. System-level benchmarking with several circuits show up to 55% reduced footprint, 25% shorter wire length, and 18% lower power with TR-L M3D vs. 2D CMOS.


international conference on computer aided design | 2016

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

Sandeep Kumar Samal; Deepak Nayak; Motoi Ichihashi; Srinivasa Banna; Sung Kyu Lim

In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL) interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study the routing overhead and delay degradation caused by tungsten BEOL interconnect in the bottom-tier of M3D. Our study shows that tungsten BEOL reduces performance by up to 30% at 4× resistance increase of bottom-tier interconnect. In addition, the bottom-tier BEOL adds a routing overhead to 3D nets, which is neglected in the state-of-the-art flow. Next, we develop two partitioning methods targeted specifically towards BEOL impact reduction. Our path-based approach identifies critical timing paths and places their cells in the top-tier to reduce the impact of delay degradation and routing overhead. Our net-based partitioning methodology confines the nets with long 2D wirelength into the top-tier to reduce the overall routing demand, and hence the metal layer usage in the bottom-tier. This in turn results in BEOL cost savings. Using a foundry 22nm FDSOI technology and full-chip GDS designs, we achieve tolerance of up to 4× increase in the bottom-tier BEOL resistance using our partitioning strategy. In addition, we save up to 3 metal layers in the bottom-tier of our M3D designs with up to 32% power savings over 2D IC for an interconnect dominated benchmark.


ieee soi 3d subthreshold microelectronics technology unified conference | 2016

Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology

Sandeep Kumar Samal; Deepak Nayak; Motoi Ichihashi; Srinivasa Banna; Sung Kyu Lim

In this paper, we conduct a comprehensive design comparison of 2D ICs, monolithic 3D ICs and TSV-based 3D ICs using a silicon-validated 14nm FinFET foundry technology and commercial quality designs. Through full-chip layouts and sign-off analysis using commercial-grade tools, the potential of monolithic 3D IC is explored and validated in terms of power, performance and area against that of TSV-based 3D ICs and 2D ICs.


international symposium on low power electronics and design | 2016

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions

Sandeep Kumar Samal; Deepak Nayak; Motoi lchihashi; Srinivasa Banna; Sung Kyu Lim

In this paper we study the impact of low thermal budget process on design quality in monolithic 3D ICs (M3D). Specifically, we quantify how much the tier-to-tier transistor performance difference affects full-chip power and performance metrics in a foundry 14nm FinFET technology. Our study first shows that 5%, 10%, and 15% top-tier device degradation in a wire-dominated, timing-closed monolithic 3D IC design leads to 7%, 12%, and 18% full-chip timing violation, respectively. Next, we address this impact with our CAD solution named Tier-Aware M3D (TA-M3D) flow that identifies potential timing-critical paths and partitions them into the faster (bottom) tier to minimize the top-tier degradation impact. One unique challenge in timing closure in this case, is how to conduct buffering and sizing on the paths that lie entirely in the top or bottom-tier as well as those that span both tiers. Our approach handles all 3 types of paths carefully and closes timing under the given top-tier degradation assumption, while minimizing the total power consumption. Our enhanced monolithic 3D IC designs, even with 5%, 10%, and 15% slower transistors in the top-tier, still offers 26%, 24%, and 5% power savings over 2D IC, respectively. Our study also covers other types of circuits.


international electron devices meeting | 2016

A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

Jiajun Shi; Deepak Nayak; Srinivasa Banna; Robert Fox; Srikanth Samavedam; Sandeep Kumar Samal; Sung Kyu Lim

Monolithic 3D IC (M3D) shows degradation in performance compared to 2D IC due to the restricted thermal budget during fabrication of sequential device layers. A transistor-level (TR-L) partitioning design is used in M3D to mitigate this degradation. Silicon validated 14nm FinFET data and models are used in a device-to-system evaluation to compare the TR-L partitioned M3Ds (TR-L M3D) performance against the conventional gate-level (G-L) partitioned M3Ds performance as well as standard 2D IC. Extensive cell-level and system-level evaluation, including various device and interconnect process options, shows that the TR-L M3D provides up to 20% improved performance while still maintaining around 30% power saving compared to standard 2D IC. Additionally, the TR-L partitioning design enables M3D with a simplified process flow that leads to 23% lower cost compared to that of G-L partitioning scheme.


international conference on simulation of semiconductor processes and devices | 2015

Impact of gate oxide complex band structure on n-channel III–V FinFETs

Dax M. Crum; Amithraj Valsaraj; Leonard F. Register; Sanjay K. Banerjee; Bhagawan Sahu; Zoran Krivakopic; Srinivasa Banna; Deepak Nayak

FinFET geometries have been developed for the sub-22 nm regime to extend Si-CMOS scaling via improved electrostatics compared to planar technology. Moreover, engineers have incorporated high-k oxide gate stacks. Beyond leakage current, less discussed is the impact of the gate oxides complex band structure on the device performance. However, it defines the boundary condition for the channel wavefunction at the interface, which, in turn, affects the quantum confinement energy for channel electrons. Here we show that the ON-state performance of n-channel FinFETs may be sensitive to the oxides complex band structure, especially with light-mass III-V channel materials, such as In0.53Ga0.47As. We study this effect using an ensemble semi-classical Monte Carlo device simulator with advanced quantum corrections for degeneracy and confinement effects. Our simulations suggest that using a surface oxide with a heavy effective mass may lower the channel carrier confinement energies, mitigating unwanted quantum side-effects that hinder device performance. Ultimately, future high-k stacks may benefit from oxide gate stack heterostructures balancing effective mass and dielectric permittivity considerations.


symposium on vlsi technology | 2016

Impact of transistor technology on power savings in monolithic 3D ICs

Sandeep Kumar Samal; Deepak Nayak; Motoi Ichihashi; Srinivasa Banna; Sung Kyu Lim

In this paper, we discuss the impact of transistor technology on the power savings in monolithic 3D ICs over traditional 2D ICs. Our results are based on gate-level 3D IC partitioning and full RTL to GDSII design and analysis of a Low Density Parity Check (LDPC) benchmark circuit block with use of two different silicon validated foundry technologies. These two technologies have the same nominal operating voltage, but differ in terms of device performance, power, and gate capacitance. Our results show that monolithic 3D IC provides 37.5% more power savings for the technology with lower device power and input capacitance compared to that of a high power device technology.


Archive | 2018

SEMICONDUCTOR WAFERS WITH REDUCED BOW AND WARPAGE

Ajey Poovannummoottil Jacob; Srinivasa Banna; Deepak Nayak; Bartlomiej Jan Pawlak


Archive | 2017

LIGHT EMITTING DIODES (LEDs) WITH INTEGRATED CMOS CIRCUITS

Deepak Nayak; Srinivasa Banna; Ajey Poovannummoottil Jacob

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Sandeep Kumar Samal

Georgia Institute of Technology

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Sung Kyu Lim

Georgia Institute of Technology

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Jiajun Shi

University of Massachusetts Amherst

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Amithraj Valsaraj

University of Texas at Austin

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Csaba Andras Moritz

University of Massachusetts Amherst

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Dax M. Crum

University of Texas at Austin

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Leonard F. Register

University of Texas at Austin

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