Alan M. Kadin

Superconductor analog-to-digital converters

Ultrafast switching speed, low power, natural quantization of magnetic flux, quantum accuracy, and low noise of cryogenic superconductor circuits enable fast and accurate data conversion between the analog and digital domains. Based on rapid single-flux quantum (RSFQ) logic, these integrated circuits are capable of achieving performance levels unattainable by any other technology. Two major classes of superconductor analog-to-digital converters (ADCs) are being developed - Nyquist sampling and oversampling converters. Complete systems with digital sampling at rates of /spl sim/20 GHz and above have been demonstrated using low-temperature superconductor device technology. Some ADC components have also been implemented using high-temperature superconductors. Superconductor ADCs have unique applications in true digital-RF communications, broadband instrumentation, and digital sensor readout. Their designs, test results, and future development trends are reviewed.

A superconductor high-resolution ADC

This paper presents the development of an Analog-to-Digital Converter (ADC) based on a low-temperature superconductor (Nb) chip and room-temperature interface modules for applications in digital receivers for communications, radars, and electronic warfare. The ADC design, MATLAB/sup TM/ simulations, and experimental results of single- and two-tone tests are described.

Retargeting RSFQ cells to a submicron fabrication process

There is a desire to move current state-of-the-art niobium Josephson IC fabrication processes (/spl sim/3 /spl mu/m) to smaller sub-micron linewidths in order to realize a decrease in gate size and increase in both speed and packing density. However, cost and time dictates that a way be found to reuse the existing RSFQ gate/cell development that has been done at the 3-/spl mu/m level. Cell retargeting is the process of migrating existing designs to a new technology, with the effort focused on the maximum reuse of existing material. We have investigated a number of issues critical to this process, including both the physical and electrical aspects. Comments are made on methodologies for RSFQ cell retargeting with respect to existing reduced-linewidth JJ fabrication processes. Experimental demonstrations are shown for retargeted RSFQ static digital frequency dividers (toggle flip-flops) operating at 220 GHz, 240 GHz, and 395 GHz.

Can RSFQ logic circuits be scaled to deep submicron junctions

Scaling of niobium RSFQ integrated circuit technology to deep submicron dimensions (linewidths of 300 nm or less) should permit increased clock rate (up to 250 GHz) and increased areal density of Josephson junctions (up to 1 million junctions/cm/sup 2/), without the need for external shunt resistors. It is shown how existing circuit layouts can be scaled down to these dimensions, while maintaining the precise timing essential for correct operation. Additional issues related to the practical realization of such circuits are discussed, including effects of self-heating and models for the generation and propagation of sub-ps single-flux-quantum pulses.

Integration of cryocooled superconducting analog-to-digital converter and SiGe output amplifier

HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.

Effects of superconducting return currents on RSFQ circuit performance

Complex RSFQ circuits are typically dc-biased with one or more current bias trees, with current returning through a superconducting ground plane. As the bias currents become larger in more complex circuits, it is increasingly critical to pay attention to the distribution of these return currents, and the effects of the resulting magnetic fields on the performance of the RSFQ circuits. We have modeled the current and field distributions, and found that magnetic field and flux are indeed significant. This has been confirmed by direct measurement using a distribution of SQUIDs. Furthermore, we have measured the performance of several RSFQ circuits, and have found that currents in the ground plane can significantly affect performance margins. Approaches to circuit and system designs that can reduce these problems are discussed.

Current Leads and Optimized Thermal Packaging for Superconducting Systems on Multistage Cryocoolers

Packaging of a superconducting electronic system on a compact multistage cryocooler requires careful management of thermal loads from input and output leads, in order not to exceed the heat lift capacity of the various stages of the cooler. In particular, RSFQ systems typically require a large total bias current or greater. A general analysis of resistive wires shows that the tradeoff between heat flow and Joule heating yields a minimum heat load from optimized bias leads on a low- stage, given by , where is the thermalization temperature of the leads on the previous (hotter) stage. This is independent of the material, number, and geometry of the leads, as long as the total lead resistance is optimized. A similar tradeoff between heat flow and signal attenuation can be applied to the optimization of high-frequency input/output lines. Superconducting leads are not subject to these limitations, and can result in further reduction in heat load. Design examples are presented for an RSFQ-based radio receiver on either a two-stage or a four-stage cooler.

Superconductor analog-to-digital converters and their applications

A wide variety of applications, ranging from radio-frequency (RF) receivers for broadband communications and signal detection, on earth and in space, would benefit from high-performance superconductor analog-to-digital converters (ADCs), based on magnetic flux quantization and fast switching Josephson junctions. Superconductor ADCs are capable of very high sample rates (100 GHz or more), very high linearity, and high sensitivity. Nyquist-rate ADCs use the high sample rate to digitize a wide instantaneous bandwidth (tens of GHz) and are useful for wideband spectrum monitoring as well as high-end scientific instrumentation. Delta and delta-sigma oversampling ADCs use the high linearity to achieve programmable trade-off between dynamic range and instantaneous bandwidth. These lowpass and bandpass ADCs have been used for direct digitization of narrower (tens to hundreds of MHz) RF bands in the 1–20 GHz range for a variety of communications, intelligence, electronic warfare, and radar applications. Another application area of these cryogenic ADCs is for outputs of cryogenic sensor arrays and terahertz mixers. Recent advances in various classes of ADCs for different applications are described.

Integration of a 4-Stage 4 K Pulse Tube Cryocooler Prototype With a Superconducting Integrated Circuit

A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a Nb IC test chip, with cells that include a high-speed rapid single flux quantum (RSFQ) binary counter. For 650 W total compressor power, extended stable operation of the counter at T=4.5 K was demonstrated with a clock frequency up to 46 GHz, with 25 mW of excess cooling capacity on the coldest stage. The thermodynamic, electromagnetic, and mechanical performance are promising for the development of an improved compact cryocooler for practical superconducting electronic applications in fields such as wireless communications.

Rebooting Computing and Low-Power Image Recognition Challenge

“Rebooting Computing” (RC) is an effort in the IEEE to rethink future computers. RC started in 2012 by the co-chairs, Elie Track (IEEE Council on Superconductivity) and Tom Conte (Computer Society). RC takes a holistic approach, considering revolutionary as well as evolutionary solutions needed to advance computer technologies. Three summits have been held in 2013 and 2014, discussing different technologies, from emerging devices to user interface, from security to energy efficiency, from neuromorphic to reversible computing. The first part of this paper introduces RC to the design automation community and solicits revolutionary ideas from the community for the directions of future computer research. Energy efficiency is identified as one of the most important challenges in future computer technologies. The importance of energy efficiency spans from miniature embedded sensors to wearable computers, from individual desktops to data centers. To gauge the state of the art, the RC Committee organized the first Low Power Image Recognition Challenge (LPIRC). Each image contains one or multiple objects, among 200 categories. A contestant has to provide a working system that can recognize the objects and report the bounding boxes of the objects. The second part of this paper explains LPIRC and the solutions from the top two winners.