Du Chen

CMP Thread Assignment Based on Group Sharing L2 Cache

With the development of electric technology, uniprocessor is being substituted by CMP (chip multi processors). CMP can run multi-thread program efficiently, many researchers engage in the study of multi-thread, including extracting multi-thread from legacy single thread program and making standardization for future multi-thread program. Data communication among threads is an inevitable problem in multi-thread program, and efficient data sharing is an important aspect for program performance. But researchers focus data sharing on memory organization and relationship among threads, there is little attention for intra-processor. In this paper, we develop a thread assignment method for group sharing L2 cache architecture according to the data relationship among threads. We allocate some threads to some cores and some threads others. In our experiment, we simulates four threads with different degree data sharing and running in four cores CMP, whose cores is divided into two groups. Comparing some program execution tracks, we find that the main difference between two simulations is the hit rate of L2 cache and thread assignment brings 6.25% running time improvement. The L2 cache hit rate is 91.0% and 87.1% with thread assignment our proposed, but the L2 cache hit rate is 77.0% and 75.4% with random thread assignment. It descends 14.0% and 11.7% for each group.

A Novel Approach for Finding Candidate Locations for Online FPGA Placement

Reconfigurable computing (RC) has been viewed as an efficient solution to achieve high performance and flexibility. Hardware tasks can be dynamically placed on and removed from reconfigurable platforms. Field-programmable gate arrays (FPGA) provide partially runtime reconfiguration (PRTR) at runtime. However, this reconfiguration will lead to more time overhead. An efficient algorithm to manage empty space is necessary for online task placement on a PRTR FPGA. This paper first proposes a data structure to maintain information about the available free area and then presents a novel approach to find candidate locations for online FPGA placement. Experimental results show that the approach proposed here is better than similar approaches to find locations for task placement.

A Performance Model for Run-Time Reconfigurable Hardware Accelerator

The reconfigurable devices such as CPLD and FPGA become more popular for its great potential on accelerating applications. They are widely used as an application-specified hardware accelerator. Many run-time reconfigurable platforms are introduced such as the Intel® QuickAssist Technology. However, its time consuming to design a hardware accelerator while the performance is hard to determine because of the extra overheads it involved. In order to estimate the efficiency of the accelerator, a theoretical analysis of such platforms was done in our paper. Three factors which impact the performance of the accelerator were concluded as well: speed up ratio, reconfiguration overhead and communication overhead. Furthermore, a performance model was established and an experiment on bzip2 was done to verify the model. The results showed that the models estimation is very close to the real world and the average error on the efficiencys threshold is less than 5%.

An Overview of Distance Learning on Information Security in Zhejiang University

Computer network has been in increasingly rapid development in recent years especially the prevalence of the Internet. The information exchange and transmission among the computers have become the inevitable trend in contemporary society. At the same time, information security also becomes the hot topic and is more significant in computer network. When the problems of information security are emerging, it is a great challenge that how to teach the knowledge and skills to the students in different disciplines, which have close relationship to information security. Distance learning is based on the application of computer network and related technologies in education field. Such teaching mode has higher efficiency compared with the traditional teaching mode. Many universities have adopted distance learning as one of the necessary solutions. In this paper, we describe the overview of distance learning on information security in Zhejiang University and share our experience in the curriculum design and construction. They described the curriculum design or the design of distance learning platform according to their backgrounds in research and the design target of the curriculum respectively. Their experiences will provide the effective references for the other universities, which have the potentials to design their own curricula for information security education. Distance learning has been proposed early (7) as a new mode of education. With its powerful advantages with the support of computer technology, distance learning offers a platform for self-directed learning. This platform needs fewer resources, saves in time and space, has instant content updating, provides more convenience and it has higher efficiency compared with the traditional mode of education. Distance learning provides rich personalization and friendly interfaces to the users. The students can carry on the study in the distributed physical places. (8 - 10) also discussed on how to construct the distance learning platform. In this paper, we describe the curriculum construction of information security in Zhejiang University. The architecture of this curriculum has been designed first and the remote learning has been taken into accounts. At the same time, a specific distance learning platform is designed and implemented for this curriculum. The design of the curriculum and the remote platform are complementary to each other.