Deleep R. Nair

Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters

The origin of drain disturb in NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming operation is identified. A comparative study of drain disturb under channel hot electron (CHE) and CHISEL operation is performed as a function of drain bias and temperature on bitcells having different floating gate length and junction depth. The disturb mechanism is shown to originate from band-to-band tunneling under CHISEL operation, unlike that under CHE operation that originates from source-drain leakage. The effect of technological parameters (channel doping and drain junction depth) on CHISEL drain disturb is studied for both the charge gain (erased cell) and charge loss (programmed cell) disturb modes. Fullband Monte Carlo device simulations are used to explain the experimental results. It is shown that methods for improving CHISEL programming performance (higher channel doping and/or lower drain junction depth or halo) increase drain disturb, which has to be carefully considered for efficient design of scaled cells.

CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters

The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.

Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.

Mechanism of drain disturb in SONOS flash EEPROMs

We investigate the mechanism of drain disturb in SONOS flash memory cells. Our results show that drain disturb can be a serious concern in a programmed state and is caused by injection of holes from the substrate into the nitride. We identify the key factors responsible for this to be band-to-band tunneling at the drain junction and impact ionization of the channel leakage current.

Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation

Drain disturb is studied in NOR flash EEPROM cells under CHE and CHISEL programming operation, before and after repeated program/erase (P/E) cycling. Drain disturb is shown to originate from band-to-band tunneling under CHISEL operation, unlike under CHE operation where it originates from source-drain leakage. Under identical initial programming time, CHISEL operation always shows slightly lower program/disturb (P/D) margin before cycling but similar P/D margin after repetitive P/E cycling when compared to CHE operation. The degradation of gate coupling coefficient that affects source/drain leakage and the increase in trap-assisted band-to-band tunneling seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.

The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs

In this paper, we report an extensive study of drain disturb in isolated cells under channel hot electron (CHE) and channel initiated secondary electron (CHISEL) has been identified to be initiated by band-to-band (BB) tunnelling as opposed to S/D leakage for CHE operation. This is verified by measurements under different temperature and on cells having different floating gate length (L/sub fg/). The effect of program/erase (P/E) cycling on drain distrubs is explored for different control gate bias (V/sub cg/) and V/sub d/. After cycling the program/disturb margin has been found to decrease for the charge gain mode, while it remains constant for the charge loss mode. The program/disturb margin for CHISEL operation is slightly lower compared to CHE operation under identical (initial) programming time (T/sub p/). However the margin becomes identical when compared after 100K P/E cycling.

Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling

The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 /spl mu/m.

Multi-level programming of NOR flash EEPROMs by CHISEL mechanism

Multi-level (ML) storage is becoming an important option to achieve high-density flash EEPROMs. This is done by storing different amount of charges in the floating gate (FG) to reliably distinguish different levels and treating these levels as different combination of bits. Since large amount of charges need to be stored in FG for ML operation, faster programming is required so that the overall writing speed is not compromised. In addition, this needs to be done without much increase in programming power. Recently, CHannel Initiated Secondary ELectron (CHISEL) injection was shown as an excellent low power and fast programming scheme for NOR flash EEPROMs. The performance, scalability and reliability of CHISEL were demonstrated for bi-level programming. However to the best of our knowledge, very few studies have focused on the feasibility of using CHISEL mechanism for ML programming. This paper demonstrates the performance and reliability of flash cells under ML CHISEL programming operation. Program transients show excellent self-convergence leading to accurate V/sub T/ control. Six different bitcell doping schemes were studied and optimized doping is identified based on their program and drain-disturb performance. Cycling endurance was studied on the optimized bitcell. Programmed VT levels show very little degradation, program transients retain their self-convergence, program/disturb margin remains within limit while only the erased VT level shows some degradation after 100K cycling. The impact of bitcell scaling on the performance and reliability of ML CHISEL programming is also explored.

The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs

The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.