Dhruva Acharyya

A Test Structure for Characterizing Local Device Mismatches

We present a test structure for statistical characterization of local device mismatches. The structure contains densely populated SRAM devices arranged in an addressable manner. Measurements on a test chip fabricated in an advanced 65 nm process show little spatial correlation. We vary the nominal threshold voltage of the devices by changing the threshold-adjust implantations and observe that the ratio of standard deviation to mean gets worse with threshold scaling. The large variations observed in the extracted threshold voltage statistics indicate that the random doping fluctuation is the likely reason behind mismatch in the adjacent devices

A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41 V at 295 MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8 T cell, 5.3 GHz operation at 1.2 V is achieved.

Rigorous Extraction of Process Variations for 65-nm CMOS Design

Statistical circuit analysis and optimization are critical for robust nanoscale CMOS design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, a rigorous method to extract process variations from in situ IV measurements is present. Transistor statistics are collected from a test chip fabricated in a 65-nm process. Gate length (L ), threshold voltage (Vth) and mobility (¿) are recognized as the leading variation sources, due to the tremendous process challenges in lithography, channel doping, and the stress engineering. To decompose these variations, three critical IV points from the cut-off and linear regions are identified. The extracted L , Vth and ¿ variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, accurate prediction of the change of drive current in all operation regions and process corners is achieved. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.

Rigorous extraction of process variations for 65nm CMOS design

Statistical circuit analysis and optimization are critical for robust nanoscale design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, we present a rigorous method to extract process variations from in-situ IV measurements. Transistor statistics are collected from a test chip fabricated in a 65 nm SOI process. We recognize gate length (L), threshold voltage (Vth) and mobility (mu) as the leading variation sources, due to the tremendous process challenge in lithography, channel doping, and stress. To decompose them, only three IV points are needed from the leakage and linear regions. Both L and Vth variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, we can accurately predict the change of drive current in all process corners. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.

Impedance profile of a commercial power grid and test system

An impedance profile of a commercial power grid and a tester power distribution system is developed in this paper. The profile is used to identify the measurable frequency range of the power supply transient signals generated by a chip. Several resistance-capacitance (RC) models of the power grid are analyzed to determine the impact of each capacitance type. The impedance profile of a C4-based production testing environment is then developed. The impedance profile of the combined probe card and the power grid RC models illustrates the range of frequencies that are measurable at the supply ports of the chip-under-test (CUT). The results suggest that it is possible to measure the important frequency components of a chips power supply transients in a production test environment for use in fault detection and localization procedures. Conventional testing methods are challenged by changing circuit sensitivities and emerging defect mechanisms resulting from the use of new fabrication materials in very deep submicron processes [1]. For example, the change from a subtractive aluminum process to damascene Cu may lead to more particle-related blocked-etch resistive opens. Technology scaling also increases the probability of resis-tive vias caused by incomplete etch. The additional delays introduced by these types of resistive defects in combination with increased circuit sensitivity due to shorter clock cycles, reduced timing slack, crosstalk and PWR/GND bounce increase the likelihood of random defects causing delay fails. Similarly, hardware-based fault localization is challenged by increases in chip complexity as well as additional interconnection levels and the limitations on the spatial resolution of imaging technology. The increase in difficulty and cost of performing hardware physical failure analysis is likely to move it into a sampling/verification role. These trends continue to increase the importance of developing alternative software-based fault localization procedures. We believe that power supply testing methods are well aligned with these needs and others as described in the International Technology Roadmap for Semiconductors. In our previous work, a testing method is presented for fault detection that uses correlation analysis of multiple simultaneously measured power supply transient signals [2]. The transients at each of the supply ports of a chip-under-test (CUT) are cross-correlated to reduce the adverse effects of process variations on fault detection resolution. The multiple supply port measurements are analyzed for the regional signal anomalies introduced by defects. The regression analysis technique that we propose in [3] is able to detect anomalies in the ratios of the waveform …

A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique

A physical unclonable function (PUF) is an embedded integrated circuit (IC) structure that is designed to leverage naturally occurring variations to produce a random bitstring. In this paper, we evaluate a PUF which leverages resistance variations which occur in transmission gates (TGs) of ICs. We also investigate a novel on-chip technique for converting the voltage drops produced by TGs into a digital code, i.e., a voltage-to-digital converter (VDC). The analysis is carried out on data measured from chips subjected to temperature variations over the range of -40°C to +85°C and voltage variations of +/- 10% of the nominal supply voltage. The TG PUF and VDC produce high quality bitstrings that perform exceptionally well under statistical metrics including stability, randomness and uniqueness.

On-chip jitter and oscilloscope circuits using an asynchronous sample clock

We demonstrate digital circuits for measuring the jitter histograms of gigahertz clock and data signals. The circuits do not require calibration, and an asynchronous sampling technique alleviates the need for an on-chip sample clock generator with delay control. We combine measurements across swept reference voltages to create statistical clock signal and eye diagram waveforms at 6GHz and 5Gbit/s, respectively. The proposed technique produced RMS jitter measurements of 2.0ps on clock signals and 6.2ps on random data signals.

Design Considerations for PD/SOI SRAM: Impact of Gate Leakage and Threshold Voltage Variation

We present a critical study of the impact of gate tunneling currents on the yield of 65-nm partially depleted/silicon-on-insulator (PD/SOI) SRAM designs. A new gate leakage monitor structure is developed to obtain device-specific gate leakage characteristics of the SRAM cells. This allows us to explore the design space accurately with reliable process information at an early stage. By relying on supply voltage-dependent analysis, it is shown that the gate-leakage impact on the cell yield can be nonmonotonic and substantial even for nondefective devices. It is also shown that design optimizations such as increased operating voltages or shorter hierarchical bitline architecture can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield in terms of cell writability and stability. Threshold voltage variations to model random fluctuation effects are extrapolated from hardware results.

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids

Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses IDDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of IDDQ contour plots. A “family” of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.

Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF

Cryptographic and authentication applications in application-specific integrated circuits (ASICs) and FPGAs, as well as codes for the activation of on-chip features, require the use of embedded secret information. The generation of secret bitstrings using physical unclonable functions, or PUFs, provides several distinct advantages over conventional methods, including the elimination of costly non-volatile memory, and the potential to increase the number of random bits available to applications. In this paper, we propose a Hardware-Embedded Delay PUF (HELP) that is designed to leverage path delay variations that occur in the core logic macros of a chip to create random bitstrings. The bitstrings produced by a set of 30 FPGA boards are evaluated with regard to several statistical quality metrics including uniqueness, randomness, and stability. The stability characteristics of the bitstrings are evaluated by subjecting the FPGAs to commercial-level temperature and supply voltage variations. In particular, we evaluate the reproducibility of the bitstrings generated at 0°C, 25°C, and 70°C, and at nominal and ±10% of the supply voltage. An error avoidance scheme is proposed that provides significant improvement against bit-flip errors in the bitstrings.