Jong Chen

Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby

Method of making embedded flash memory with salicide and sac structure

Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices

Method for making deep sub-micron mosfet structures having improved electrical characteristics

Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory

Stack gate flash memory cell featuring symmetric self aligned contact structures

Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash

Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process

Tilt-angle ion implant to improve junction breakdown in flash memory application

Flash memory cell with vertical channels, and source/drain bus lines