Didier Celi

A computationally efficient physics-based compact bipolar transistor model for circuit Design-part II: parameter extraction and experimental results

A compact bipolar transistor model was presented in Part I that combines the simplicity of the SPICE Gummel-Poon model (SGPM) with some major features of HICUM. The new model, called HICUM/L0, is more physics-based and accurate than the SGPM but at the same time, from a computational point of view, suitable for simulating large circuits. In Part II, a parameter determination procedure is described and demonstrated for a variety of SiGe process technologies.

Characterization and Modeling of an SiGe HBT Technology for Transceiver Applications in the 100–300-GHz Range

This paper describes a methodology for extracting and verifying the high-frequency model parameters of the HICUM L0 and L2 models of a silicon-germanium HBT from device and circuit measurements in the 110-325-GHz range. For the first time, the non-quasi-static effects, missing in the HICUM/L0 model, are found to be essential in accurately capturing the frequency dependence of the transistor maximum available power gain beyond the inflection frequency for unconditional stability. Furthermore, it is demonstrated that the optimal partitioning of the area and periphery components of the junction base-emitter, base-collector, and collector-substrate capacitances, and of the internal and external base and collector resistances can only be determined from S -parameter measurements beyond 200 GHz. The extracted models are validated on state-of-the-art linear and nonlinear circuits (amplifier, voltage-controlled oscillator (VCO), and VCO + divider chain) operating at frequencies as high as 240 GHz.

Compact Layout and Bias-Dependent Base-Resistance Modeling for Advanced SiGe HBTs

In this paper, an improved and extended set of physics-based analytical equations for describing the external and internal base resistance of silicon-germanium HBTs as a function of geometry (layout) is presented. The investigated layouts include single- and double-base contacts not only in parallel but also perpendicular to the emitter finger. In addition, via and slot base contacts, a large range of link to internal-base-sheet-resistance ratio, and changes in external base layout dimensions are covered. The new equations are verified using quasi-3-D device simulation and are demonstrated to be applicable to all practically useful emitter aspect ratios.

Scalable Approach for HBT's Base Resistance Calculation

This paper presents a detailed investigation of the dual base method for intrinsic and extrinsic HBTs base resistance extraction that is of utmost importance for process monitoring and device modeling purpose. Ring emitter test structures layout, dc measurement conditions, and extraction methodology have been improved to get reliable results. A particular attention has been drawn to the external base resistance extraction and the effect of parasitic resistances is highlighted. The method has been generalized for an extraction of the base resistance specific parameters using any number of geometries (widths and lengths) and therefore demonstrates the base resistance scalability. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS SiGeC technology, and results are discussed.

Scalable approach for external collector resistance calculation

For device modelling purposes, the geometry dependence of the external collector resistance has been investigated. Firstly, the collector resistance is split into a perfectly 1D vertical resistance and a 2D horizontal contribution. Using specific test structures and DC measurements, geometry independent parameters are then extracted. An analytical scalable formula based on Fourier techniques finally computes both components for a given geometry by taking into account the current distribution in the horizontal layer. This new method is applied to a double poly BiCMOS technology and results are discussed.

New Method for Oxide Capacitance Extraction

Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results are discussed.

Implementation and quality testing for compact models implemented in Verilog-A

An overview on the implementation of new physical effects into the heterojunction bipolar transistor compact model HICUM/L2 is presented along with a description of the quality testing procedures performed before its public release for production circuit design in commercial simulators. Related topics such as potential measures for model run time improvements and failures are also discussed. Significant differences in run time for different commercial circuit simulators reflect their different approaches towards compact model implementation and solution of the non-linear circuit equation system.

Advanced extraction procedure for parasitic collector series resistance contributions in high-speed BiCMOS technologies

The parasitic collector resistance is of high importance for device performance of HBT manufactured in advanced SiGe technologies. The external collector resistance contribution RCx is a critical modeling parameter for AC and transient operation. If the collector resistance is estimated incorrectly, the RF performance of the modeled device may significantly differ from the manufactured HBT. An advanced test structure for resistance extraction is presented and measured in two different ways. The obtained resistance values and extraction results are verified using analytical equations and quasi-three-dimensional device simulations.