Paul Coene

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip

The ability to (re)schedule a task either in hardware or software will be an important asset in a reconfigurable systems-on-chip. To support this feature we have developed an infrastructure that, combined with a suitable design environment permits the implementation and management of hardware/software relocatable tasks. This paper presents the general scope of our research, and details the communication scheme, the design environment and the hardware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320/spl times/240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.

Designing an operating system for a heterogeneous reconfigurable SoC

The emerging need for large amounts of flexible computational power on embedded devices motivated many researchers to incorporate reconfigurable logic together with an instruction-set-processor (ISP) into their architectures. This implies that tomorrows applications will make use of both the ISP and the reconfigurable logic in order to provide the user with maximum performance. Today, however, a few stumbling blocks prevent these kinds of heterogeneous architectures from becoming mainstream. The technology still lacks a form of run-time management infrastructure. This infrastructure should ease application development by shielding the programmer from the complexity of the system and by providing a clear application development API. This paper presents a novel approach for designing an operating system for reconfigurable systems (OS4RS). Creating such an operating system is an integral part of our ongoing research regarding reconfigurable computing. An initial version of our operating system was used to manage a reconfigurable systems demonstrator.

Run-time support for heterogeneous multitasking on reconfigurable SoCs

In complex reconfigurable systems on chip (SoC), the dynamism of applications requires an efficient management of the platform. To allow run-time management of heterogeneous resources, operating systems (OS) and reconfigurable SoC platforms should be developed together. For run-time support of reconfigurable architectures, the OS must abstract the reconfigurable computing resources and provide an efficient communication layer. This paper presents our efforts to simultaneously develop the run-time support and the communication layer of reconfigurable SoCs. We show that networks-on-chip (NoC) are an ideal communication layer for dynamically reconfigurable SoCs, explain how our OS provides run-time support for dynamic task relocation and detail how hardware parts of the OS are integrated into the higher layers of the NoC. An implementation of the OS and of the dedicated communication layer on our reconfigurable architecture supports the concepts we describe.

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

DSP architectures often feature multiple register files with sparse connections to a large set of ALUs. For such DSPs, traditional register allocation algorithms suffer from a lot of problems, including a lack of retargetability and phase-ordering problems. This paper studies alternative register allocation techniques based on placement and routing. Different register file models are studied and evaluated on a state-of-the art coarse-grained reconfigurable array DSP, together with a new post-pass register allocator for rotating register files.

Design of Cam-E-leon, a run-time reconfigurable web camera

This paper describes the design of a reconfigurable Internet camera, Cam-E-leon, combining reconfigurable hardware and embedded software. The software is based on the µClinux operating system. The network appliance implements a secure VPN (Virtual Private Network) with 3DES encryption and Internet camera server (including JPEG compression). The appliances hardware can be reconfigured at run-time by the client, thus allowing to switch between several available image manipulation functions. The reconfiguration information is retrieved from a reconfiguration server on the network, thus allowing a flexible implementation of new services.The paper describes the hardware and software architecture of the platform, the run-time reconfiguration features of the platform including the integration of the platform in the network, and the design process followed to implement the appliance starting from a high-level executable specification.

Design of a secure, intelligent, and reconfigurable Web cam using a C based system design flow

This paper describes the design of a reconfigurable Internet camera, Cam-E-leon, combining reconfigurable hardware and embedded software. The software is based on the /spl mu/Clinux operating system. The network appliance implements a secure VPN (virtual private network) with 3DES encryption and Internet camera server (including JPEG compression). The appliances hardware can be reconfigured at run-time by the client, thus allowing us to switch between several available image manipulation functions. This paper focuses on the design process used to implement the appliance starting from a high-level executable specification.

Hardware and a Tool Chain for ADRES

Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well as on the verification process of all involved tools.

The future is dynamic: adaptive runtime resource management for heterogeneous computer platforms

Software developers increasingly need to take advantage of heterogeneous hardware resources, like GPUs and DSPs, while coping with dynamic events and quality of service requirements. Our poster shows how an adaptive runtime resource manager explores resource assignment strategies to solve this problem. A real-world video processing application demonstrates the approach.

Enabling Run-time Task Relocation on Reconfigurable Systems

The ability to (re)schedule a task either in hardware or software will be an important asset in a reconfigurable systems-on-chip. To support this feature we have developed an infrastructure that, combined with a suitable design environment permits the implementation and management of hardware/software relocatable tasks. This paper presents the general scope of our research, and details the communication scheme, the design environment and the hardware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320 × 240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.