Dilip P. Vasudevan

Reversible-logic design with online testability

Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Carry-select adders are one of the faster types of adders. This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers. The multiplexers used in the adder are also totally self-checking. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed. Adders of arbitrary size can be constructed by cascading the appropriate number of such 2-bit adders. A range of adders from 4 to 128 bits is designed using this approach employing a 0.5-mum CMOS technology. The transistor overhead in implementing these self-checking adders varies from 19.51% to 20.94%, and the area overhead varies from 16.07% to 20.67% compared to adders without built-in self-checking capability.

Online testable reversible logic circuit design using NAND blocks

A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.

A novel approach for on-line testable reversible logic circuit design

Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.

A technique for modular design of self-checking carry-select adder

The carry-select adders provide significant speed improvement over other types of adders. This paper proposes a new approach for constructing self-checking carry-select adders set of faults online. Adders of arbitrary size can be constructed by simply cascading the appropriate number of 2-bit adders. A range of adders from 4 bit to 128 bits was designed using this approach employing a 0.5/spl mu/m CMOS technology. The area needed for implementing the self-checking adders is 16.07 % to 20.67% more than that required in adders without built-in self-checking capability.

Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing

3D integration is a promising technology that provides high memory bandwidth, reduced power, shortened latency, and smaller form factor. Among many issues in 3D IC design and production, testing remains one of the major challenges. This paper introduces a new design-for-test technique called 3D-GESP, an efficient Built-In-Self-Repair (BISR) algorithm to fulfill the test and reliability needs for 3D-stacked memories. Instead of the local testing and redundancy allocation method as most current BISR techniques employed, we introduce a global 3D BISR scheme, which not only enables redundancy sharing, but also parallelizes the BISR procedure among all the stacked layers of a 3D memory. Our simulation results show that our proposed technique will significantly increase the memory repair rate and reduce the test time.

Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations

Leakage power is becoming the dominant power domponent in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 8T SRAM cell design considering these leakage and stability issues is proposed in this paper. Higher read static noise margin (SNM) compared to conventional 6T SRAM is achieved. The proposed SRAM is compared with a recently reported low power 8T,9T designs and the conventional 6T SRAM. Lower area compared to the 9T design and lower power consumption compared to conventional 6T, 8T and the 9T designs are reported. The adiabatic operation of this design provides further reduction in power compared to the non-adiabatic operation. The average power of the designs with process variation at 65 and 45nm processes are also reported. Power reduction of the order of 10 times (90 – 91%) is reported with the proposed design.

CMOS realization of online testable reversible logic gates

Three reversible logic gates that can be used to implement reversible digital circuits with various levels of complexity are proposed. The major feature of these gates is that they provide online-testability for circuits implemented using them. The CMOS realization of these gates is presented in this paper.

Ultra Low Power Booth Multiplier Using Asynchronous Logic

Asynchronous logic shows promising applicability in ASIC design due to its potentially low power and high robustness properties. For deep submicron technologies the static power is becoming very significant and many applications require that this power component to be reduced. A new logic called Positive Feedback Charge Sharing Logic (PFCSL) is proposed, which reduces both dynamic and especially static power and also could be implemented with asynchronous logic. This new logic combines adiabatic logic with charge sharing technology avoiding the penalty of power clock generator. A novel 16-by-16-bit Radix-4 Booth Multiplier is built based on PFCSL and implemented in 45nm technology. We achieve around 30% reduction in dynamic power and 60% in static power respectively compared to the same design being implemented using static dual-rail logic. Also, the area of the multiplier is significantly smaller.

Ultra Low Power Asynchronous Charge Sharing Logic

Asynchronous logic enables significant power reduction and high robustness in digital design. In this paper, a novel Asynchronous Charge Sharing Logic (ACSL) is proposed to achieve ultra-low dynamic and static power with little trade-off in performance. ACSL combines adiabatic logic with charge sharing technology so that the penalty of power clock generator in adiabatic circuit is eliminated while nearly 50% energy transferring efficiency is obtained. Also, by discharging all internal nodes to ground in idle mode, a saving of 75% of static power of a one-bit full adder is achieved while compared to the popular Domino Differential Cascode Voltage Switch Logic (DDCVSL) adder. Some 8-bit multipliers are built based on ACSL, PFAL (Positive Feedback Adiabatic Logic), DDCVSL and dual-rail Domino logic. All our implementations results are reported for the 45 nm CMOS process. At least 30% dynamic power reduction and more than 24% improvement of the Power-Delay Product are achieved compared to other three types of logic. Significant leakage power reductions of more than 30% can be also achieved.