James Patrick Parkerson

Reversible-logic design with online testability

Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Carry-select adders are one of the faster types of adders. This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers. The multiplexers used in the adder are also totally self-checking. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed. Adders of arbitrary size can be constructed by cascading the appropriate number of such 2-bit adders. A range of adders from 4 to 128 bits is designed using this approach employing a 0.5-mum CMOS technology. The transistor overhead in implementing these self-checking adders varies from 19.51% to 20.94%, and the area overhead varies from 16.07% to 20.67% compared to adders without built-in self-checking capability.

Online testable reversible logic circuit design using NAND blocks

A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.

Embedded thin film resistors, capacitors and inductors in flexible polyimide films

The High Density Electronics Center (HiDEC) at the University of Arkansas is working with the Sheldahl MCM-L Consortium and Rensselaer Polytechnic Institute (RPI) to develop low-cost embedded resistors, capacitors, and inductors in flexible polyimide films under an ARPA contract. Embedding thin-film passive devices into polyimide layers as part of a Multichip Module (MCM) system is new. The design concept allows fabrication and testing of embedded passive devices before assembling them into an MCM-L substrate. Embedded passive devices are needed as an enhancement to present day MCM-L and MCM-D technologies. The ability to remove devices such as terminating resistors and decoupling capacitors from the surfaces of PCB boards and MCMs into a flexible film, at low cost, would be a break-through for MCM technology. The devices are made into a flexible MCM package using a 2 layer interconnect system called the Interconnected Mesh Power System (IMPS) developed and patented at the University of Arkansas. The IMPS interconnection topology incorporates fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. The materials being used are NiCr, TaN, and CrSi for the resistors and Ta/sub x/O/sub y/ and BaTiO/sub x/ for the capacitors. Contacts, interconnecting signal lines, and power lines are made with Cu metallurgy. The devices are made on a 25 /spl mu/m or 50 /spl mu/m thick polyimide film and are encapsulated with the same polyimide.

On self-healing digital system design

In recent years there has been a significant growth of interest in exploiting the principles of biological processes to create powerful methodologies for solving computational problems. This paper discusses how these features have been exploited in digital hardware design. It also introduces an architecture for implementing self-healing digital systems that is inspired by the antigen protection mechanism employed by the human immune system. In the proposed architecture, a spare cell is dedicated to replace one in a group of four functional cells. Once one of these four functional cells is found to be faulty, the spare cell is cloned as the faulty cell. This architecture is especially suitable for tolerating soft errors in functional cells or on interconnect lines. Another major advantage of this architecture is that the outputs of functional cells are connected to the inputs of other physically adjacent functional cells, thus making it appropriate for nanocomputing system design.

A novel approach for on-line testable reversible logic circuit design

Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.

Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects

Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long lines become highly resistive and have unacceptable delays. One possible solution to the problem of long lossy lines is to transfer these lines off-chip using seamless high off-chip connectivity (SHOCC) technology. In this work, me modeled and studied the electrical performance of SHOCC signal lines. The performance of SHOCC interconnects was compared with that of typical on-chip interconnerts. Modeling and simulation results, along with recommendations with regards to driver sizes and the type of interconnect that should be used, are presented.

CMOS realization of online testable reversible logic gates

Three reversible logic gates that can be used to implement reversible digital circuits with various levels of complexity are proposed. The major feature of these gates is that they provide online-testability for circuits implemented using them. The CMOS realization of these gates is presented in this paper.

Design considerations for using integrated passive components

The demand for smaller, lighter, faster and less expensive electronic products has led to the development of a laminate multi-chip module (MCM-L) process that contains integrated passive components. The University of Arkansas (UA) cooperated with Sheldahl Corporation and the Rensselaer Polytechnic Institute (RPI), as a member of the DARPA funded MCM-L consortium, to develop this integrated passive MCM-L (IPMCM-L) process. It contains resistors, capacitors and inductors integrated in a flexible film. Parasitic extraction, modeling, and simulation must be performed to effectively utilize this process for high performance circuits. A design methodology addressing these issues is discussed along with the process layers and example device layouts.

Electrical characterization of multilayered thin film integral passive devices

Current high performance multichip microelectronic packaging requires high density interconnects (<50 /spl mu/m interconnect lines and spaces), integral passive devices (those embedded within the package), and multilayering technologies. The University of Arkansas High Density Electronics Center (HiDEC) and Sheldahl Inc., have developed a high density interconnect adhesiveless metallized film substrate technology for these high performance microelectronic packaging applications. The development of multilayered thin film integral passive devices on polyimide substrates for high frequency applications (>500 MHz) is required in the electronics packaging industry. Factors driving the passive integration technology are overall system miniaturization and higher operating frequencies. With the increasing demands for miniaturization in electronic packaging, the need for miniaturization of passive devices is evident and the precise characterization of these devices is extremely important in application development. This paper describes the design considerations required for producing multilayered passive devices and the frequency dependent characteristics of multilayered resistors, capacitors, inductors, and tuned circuits. Results indicate that this new multilayered integral passives technology has the potential for denser packaging, higher reliability, lower cost, and future replacement of many surface mount devices.