Dimitri Soussan

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing

A 32b SoC is designed in 28nm FDSOI to operate in either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) mode, at 0.33V, with process-temperature compensation. At near threshold, it overcomes low transistor current at negative temperatures, the need for an extra digital supply IO, and the clocking power costs faced by the internet-of-things (IoT) and wearable systems. The system includes: 1) an all-digital single-supply open-loop clock multiplier achieving 1.51 pJ/cycle; 2) a 0.33V/0.45V dual-mode switched-network-capacitor DC-DC down converter from a 1.1V logic supply, reaching 75% conversion efficiency in both modes; 3) a closed-loop low-invasiveness timing monitoring system dynamically compensating device centering and temperature changes, enabling constant frequency operation down to -40°C at 20MHz (1MHz) in EE (LL) mode. The system fully exploits forward body bias (FBB) available in 28nm UTBB FDSOI with LVT transistors.

SER/SEL performances of SRAMs in UTBB FDSOI28 and comparisons with PDSOI and BULK counterparts

This work presents alpha and neutron SER characterizations of a 28nm commercial Fully-Depleted SOI technology predisposed to consumer applications. Its intrinsic SER hardness is as well compared to known highly reliable Partially-Depleted SOI technologies.

Experimental Soft Error Rate of Several Flip-Flop Designs Representative of Production Chip in 32 nm CMOS Technology

This paper shows alpha experimental Soft Error Rate characterization of several standard and hardened Flip-Flop architectures processed in a 32 nm technology. It showsthe effecton the alpha Soft Error Rateof experimental parameters such as algorithm (static vs.kdynamic), data filling the register, etc. 12 data patterns onmore than 5Flip-Floptypes(including DICE-like design)are reported in this articlein order to help the radiation engineer to choose the best algorithm/pattern for its SER characterizations.

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

A 32kb memory is presented with an Ultra Low Voltage optimized 10 transistors bitcell designed to withstand an extended voltage range from 1.2V down to 0.35V, achieving 1.77pJ low energy access. A validation circuit was fabricated in 65nm CMOS and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts show 0.32V minimum voltage at 490kHz and up to 17X energy gain per operation. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling future medical appplications radiation reliability through bit-interleaving combined with error correcting code.

Alpha soft error rate of FDSOI 28 nm SRAMs: Experimental testing and simulation analysis

We report on soft error rate measurements on 28 nm commercial FDSOI SRAM bitcells under alpha irradiation. The technology proves to be experimentally quasi-immune to alpha particles. Simulation results are also presented, through 3D-TCAD investigations of the transport mechanisms followed by Monte-Carlo simulations of the charge deposition.

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors

This paper presents the technology and design optimization performed in 28nm FD-SOI to reach ultra-low energy and/or soft-error tolerance on ARM® Cortex®-M4 32bits processors. A 8.9pJ per cycle efficiency was measured while performing at 0.5V/45MHz, and a soft-error immunity was measured under alpha and neutron radiation while performing at 1.0V/730MHz. These results were achieved by the design of specific standard cells, macros and clock tree architectures, the technology intrinsic performances, and an adapted CAD flow.

A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing

A mixed analog/digital impedance calibration circuit for LPDDR2 transmitter is proposed, taking advantage of the Fully Depleted SOI technology and its back biasing capability. This feature allows to modulate the current, and hence the impedance of the output driver. While the process deviation is compensated digitally, the proposed technique gives the opportunity to compensate for temperature and voltage drifts during transmission thanks to back biasing control.

A low jitter active body-biasing control-based output buffer in 65nm PD-SOI

This paper proposes a specific low jitter and high speed Ouput interface which takes advantage of the Partially Depleted Silicon-on-Insulator technology while avoiding its drawbacks related to floating body effects. Thanks to an active body-biasing control technique, the additional jitter related to PD-SOI history effect, as well as the higher static leakage current compared to bulk technology, are more than compensated. In depth analyses are presented to highlight the robustness of this technique with respect to the other solutions considering various capacitive loads and temperatures.

On-Orbit Upset Rate Prediction at Advanced Technology Nodes: a 28 nm FD-SOI Case Study

We address accurate computation of on-orbit upset rates in advanced technologies, with a focus on FD-SOI at the 28 nm node. Heavy-ion measurements performed on FD-SOI SRAM bit-cells give experimental evidence of the technology’s intrinsic robustness in space environments; this extreme reduction of sensitive volume dimensions deeply affects the assumptions pertaining to the radiation response models used to predict upset rates. The generic “Integral Rectangular ParallelePiped” (IRPP) model, although requiring careful setting of its parameters, provides us with first-order estimates of the error rate. We then present a custom FD-SOI response model within our Monte-Carlo simulation chain, enabling comparison with IRPP and further analyses.

30% static power improvement on ARM Cortex ® -A53 using static Biasing-Anticipation

This paper presents an energy efficiency improvement methodology based on the use of additional static biasing instead of margins during design stage. While the impact of margins used to prevent unsystematic process limitations cannot be recovered after fabrication, using biasing anticipation offers the possibility to enable the degradation recovery only when it is required. A CAD study on ARM Cortex®-M4 Microcontrollers (MCU) showed up to 50% of static current reduction at typical corner, nominal voltage, compared to the margin-based methodology. An implementation of a 1GHz ARM Cortex®-A53 core in 28nm fully-depleted silicon-on-insulator (FD-SOI) was performed using this methodology, and silicon measurements on 60 dies confirmed up to 30% median static power improvements.