Dipu Pramanik

Stress-Aware Design Methodology

Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations

Optimizing boron junctions through point defect and stress engineering using carbon and germanium co-implants

We report the fabrication of p+∕n junctions using Ge+, C+, and B+ co-implantation and a spike anneal. The best junction exhibits a depth of 26nm, vertical abruptness of 3nm∕decade, and sheet resistance of 520Ohm∕square. The junction location is defined by where the boron concentration drops to 1018cm−3. These junctions are close to the International Technology Roadmap specifications for the 65nm technology node and are achieved by careful engineering of amorphization, stresses, and point defects. Advanced simulation of boron diffusion is used to understand and optimize the process window. The simulations show that the optimum process completely suppresses the transient-enhanced diffusion of boron and the formation of boron-interstitial clusters. This increases the boron solubility to 20% above the equilibrium solid-state solubility.

Bringing Manufacturing into Design via Process-Dependent SPICE Models

This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full range of process parameter variations. The process-dependant SPICE models allow direct access to process parameter variations in circuit design. The extracted models are employed in rudimentary digital circuits to investigate the delay variation in response to process deviations. The proposed approach significantly improves design-for-manufacturing (DFM) by allowing for accurate design sensitivity analysis and parametric yield assessment, as a function of statistically independent and measurable process variations

Modeling Process Impact on Cu/Low k Interconnect Performance and Reliability

This paper studies the impact of layout alteration and structural variation on capacitance and spatial variations of electric and thermal mismatch stress fields. The fabrication process related layout alteration and structural variation include floating dummy fill insertions, silicon nitride cap layers thickness selections, and metal line cross-section shape changes. It is demonstrated that the spatial distributions of electric field and thermal-mechanical stress field have different geometric dependence and process variations have different implications. The layout pattern and interconnect architecture that are optimized for electric performance may be inferior in reliability due to large stress concentrations. The numerical results suggest that in pursuit of manufacturability the tradeoffs between electrical performance and mechanical reliability need to be considered together for future interconnect architecture and process technology developments.

Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects

The layout dependence of process stress in Cu/low k interconnects are examined using various stress sources and layout patterns. The anisotropic grain growth stress model is compared with the conventional isotropic intrinsic stress model and the latter is found to underestimate stress concentrations in the dielectric regions near metal line ends. Both the grain growth stress in copper and the thermal mismatch stress in copper and low k dielectrics are considered in the layout dependence study. The results demonstrate that accurate stress evaluation in interconnect structures has to employ geometrical models that include layout variations. Capabilities are developed to extract these geometrical models directly from layout analysis.

Ultra-Shallow Junctions for the 65nm Node Based on Defect and Stress Engineering

The co-implantation of germanium, carbon, and boron with the optimum implant energies and doses makes it possible to create p + /n junctions with the sheet resistance of less than 600 Ohm/square and the slope of less than 3 nm/decade. The narrow process window is based on careful engineering of the amorphization, point defects, and stresses and includes standard 1050°C spike annealing. The germanium pre-amorphization suppresses the ion channeling for the subsequent boron implant. The tensile stress induced by the substitutional carbon atoms and the compressive stress induced by the substitutional germanium atoms slow down boron diffusion and help to make the junctions shallower. The stress gradient in the transition region from the strained carbon and germanium doped layers to the relaxed silicon underneath creates an uphill boron flux that makes the junction slope steeper. The optimum amount of carbon is placed in between the implanted boron and the implant damage, which is located below the amorphized layer. During the annealing, the carbon atoms capture silicon interstitials that are coming from the implant damage and form carbon-interstitial clusters. The analysis demonstrates that it is possible to capture over 95% of the interstitials this way before they have a chance to reach boron-doped layer. This completely suppresses the transient-enhanced boron diffusion (TED) and drastically reduces the amount of boron that is deactivated in boron-interstitial clusters (BICs). In fact, the point defect engineering with an optimized carbon profile allows to remove all non-equilibrium silicon interstitials that are generated by the following three sources: the implant damage below the amorphized layer, the rapid temperature ramp down, and the interstitials generated by boron at high concentrations (due to the effect known as boron-enhanced diffusion (BED)). The latter effect leads to significant increase of the apparent boron activation level beyond the well-characterized solid-state solubility level. We explain this effect as a reduction in formation of BICs due to the lack of interstitial supersaturation. In carbon-free silicon, high concentration boron is always accompanied by the non-equilibrium interstitials, coming from either the implant damage or the BICs even if boron is introduced into silicon by pre-deposition instead of the implantation. Extensive experiments and theoretical analysis based on simulation of the interaction of Ge, C, I, and B atoms, as well as the stress effects, point to the optimized process flow that improves the shape and parameters of the p + /n USJs.

Determination of Cu-line EM Lifetime Criteria Using Physically Based TCAD simulations

A physically based simulation methodology provides fast and practical EM lifetime prediction. We identified an “EM-aware” region to define the length dependence of Cu-lines under high current stress. For eventual calibration of 2× nm node Cu-lines, we analyzed the sensitivity trends of vacancy and void profiles as well as the mass transport mechanisms using a 3D TCAD tool. This includes electron flow dependency to explain line and via depletion effects for void formations under various EM stress conditions. We report a non-linearity in the length dependence on the EM failure jL product at ~9000 A/cm and a slight temperature dependence on the Blech Threshold (jL)c at ~2000 A/cm extracted at 300°C in the EM aware region.

Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

The industry trend towards smaller feature size and higher integration density leads to multi-level Cu/low-k interconnect schemes with reduced line width and spacing. Mechanical stress is generated during interconnect fabrication. The spatial distribution of the stress is strongly affected by the layout variation. The packaging process generates a global chip level stress that permeates to the local interconnect level. Stress related failures and yield loss are major areas of concern for Cu/low-k interconnects. The effects of fabrication process, layout variation, and packaging process on the final stress distributions in Cu/low-k interconnect structures are examined and the reliability impact of mechanical stress is assessed.

Effect of Process and Layout on Strain Enhancement from Dual Stress Liners

Tensile and compressive stressed nitride liners have been used to increase the carrier mobility in n-channel and p-channel silicon transistors respectively. Simulations indicate how much of the stress in the film is transferred to the channel region and the magnitude of the stress in different directions. A simple bulk piezoresistive model was used to estimate the effect on carrier mobility. It is shown in the case of the n-channel transistors that the enhancement is due to the vertical stress component whereas in the case of p-channel devices the enhancement is due to the in-plane stresses. The effect of different process conditions such as film stress, thickness and method of deposition, on mobility enhancement, was also characterized. It is shown that the enhancement saturates with increasing nitride thickness but scales proportionally with the film stress. Detailed studies of the effect of the circuit layout on the final channel stress allow the critical layout parameters to be identified. The variation of device performance with the layout parameters is quantified and can be used to define design rules as well as equations to modify the device characteristics based on layout.