Lars Bomholt

Bringing Manufacturing into Design via Process-Dependent SPICE Models

This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full range of process parameter variations. The process-dependant SPICE models allow direct access to process parameter variations in circuit design. The extracted models are employed in rudimentary digital circuits to investigate the delay variation in response to process deviations. The proposed approach significantly improves design-for-manufacturing (DFM) by allowing for accurate design sensitivity analysis and parametric yield assessment, as a function of statistically independent and measurable process variations

New integrated Monte Carlo code for the simulation of high-resolution scanning electron microscopy images for metrology in microlithography

A new Monte Carlo code is presented that includes among others definition of arbitrary geometries with sub-nanometer resolution, high performance parallel computing capabilities, trapped charge, electric field calculation, electron tracking in electrostatic field, and calculation of 3D dose distributions. These functionalities are efficiently implemented thanks to the coupling of the Monte Carlo simulator with a TCAD environment. Applications shown are the synthesis of SEM linescans and images that focus on the evaluation of the impact of proximity effects and self charging on the quantitative extraction of critical dimensions in dense photoresist structures.

A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology

For the 65 nm technology node and beyond, new manufacturability problems are arising that strongly impact device and circuit behavior. Among these problems, line-edge and line-width roughness (LER and LWR) are of particular interest as dominant issues affecting parametric yield. In this paper, we investigate LWR effects by applying latest generation, full 3D TCAD technology including lithography simulation. In addition, our results answer open questions concerning the applicability of 2D slicing approximations vis a vis a 3D modeling effort. While LWR has been investigated by TCAD before, our methodology includes a full 3D process simulation (including lithography) without simplifications to generate the final transistor structures

Large scale model of wafer topography effects

A technique traditionally used for optical proximity correction (OPC) is extended to include topography proximity effects (TPE). Central to this is a thin-mask imaging model capable of addressing very large areas. This compact model being compatible with traditional fast imaging models used in OPC can then be used in standard correction approaches, compensating for both the optical proximity effects and wafer topography proximity effects. Model origin and model form are considered along with calibration process. Capturing ability and performance of the model are numerically evaluated on a number of test patterns. The performance of the model is close to that of models used in the planar case.

Predictive modeling for EBPC in EBDW

We demonstrate a flow for e-beam proximity correction (EBPC) to e-beam direct write (EBDW) wafer manufacturing processes, demonstrating a solution that covers all steps from the generation of a test pattern for (experimental or virtual) measurement data creation, over e-beam model fitting, proximity effect correction (PEC), and verification of the results. We base our approach on a predictive, physical e-beam simulation tool, with the possibility to complement this with experimental data, and the goal of preparing the EBPC methods for the advent of high-volume EBDW tools. As an example, we apply and compare dose correction and geometric correction for low and high electron energies on 1D and 2D test patterns. In particular, we show some results of model-based geometric correction as it is typical for the optical case, but enhanced for the particularities of e-beam technology. The results are used to discuss PEC strategies, with respect to short and long range effects.

Implementation of TCAD-for-Manufacturing Methodology using Process Compact Models

We report a complete TCAD methodology that addresses the considerable manufacturing challenges posed by rising technological complexity, increasing process variability and shrinking time-to-market windows. Using TCAD simulations as input, process compact models are created to enable efficient analysis of complex and multivariate process-device relationships, with applications to enhancing process manufacturability and process control. The methodology is illustrated with two case studies for 90nm CMOS and edge emitting laser technologies

Modeling of Cross-Talk Effects in Floating-Gate Devices Using TCAD Simulations

Technology CAD (TCAD) modeling is used to develop, analyze, and optimize flash memory devices under all operating conditions, taking into account three-dimensional effects such as cross-talk between the cells. A methodology for structure generation, meshing, device simulation, and characterization of flash memory devices is proposed. The results demonstrate the effectiveness of full 3D simulation models for flash memory cells, which capture the geometrical, physical, and electrostatic effects

Analysis of Process-Geometry Modulations through 3D TCAD

In this work we present a study of the combined effects of the variation of process parameters and geometry in a 65 nm technology through consistent three-dimensional TCAD process and device simulations. Channel lengths and widths together with two critical process parameters obtained through a screening experiment are examined in a 3-level full-factorial design of experiments. The results show an increased impact of process variations for short and narrow structures.

Addressing LER through atomistic self-assembly

While current and next generation lithographic techniques mostly focus on increasing resolution, line edge roughness (LER) remains one of the primary problems that limit the progress of scaling. In this paper, we examine the impact of lithographically induced line edge roughness on device performance using 3D TCAD (Technology CAD) simulation. We propose a methodology to reduce line edge roughness and examine the impact using simulation-based atomistic analysis of microscopic surface roughness. We show that several alternative wafer processing options - such as orientation dependent etching, selective epitaxy, and amorphization followed by solid phase epitaxial recrystallization - significantly reduce the lithography-induced line edge roughness. In particular, this is possible for the {111} silicon surfaces, due to their abnormally low etching and epitaxy rates compared to the other crystal orientations. For FinFETs and memory devices, this corresponds to non-standard (110) wafers with structures aligned across the <111> crystal direction. A detailed example is given on how the crystal self-assembly suppresses line edge roughness and cuts the average surface slope by a factor of four during a ten minute selective epitaxy process. The remaining surface roughness is limited to a few atomic steps and enables transistor scaling to the end of the roadmap.

Practical resist model calibration for e-beam direct write processes

With the constantly improving maturity of e-beam direct write exposure tools and processes for applications in high volume manufacturing, new challenges with regard to speed, throughput, correction and verification have to be faced. One objective of the MAGIC high-throughput maskless lithography project [1] is the application of the physics-based simulation in a virtual e-beam direct write environment to investigate proximity effects and develop comprehensive correction methodologies [2]. To support this, a rigorous e-beam lithography simulator for the feature scale has been developed [3]. The patterning behavior is determined by modeling electron scattering, exposure, and resist processing inside the film stack, in analogy with corresponding simulation capabilities for the optical and EUV case. Some model parameters, in particular for the resist modeling cannot be derived from first principles or direct measurements but need to be determined through a calibration process. To gain experience with the calibration of chemically amplified resists (CAR) for e-beam lithography, test pattern exposures have been performed for a negative tone CAR using a variable-shaped beam writer operating at 50kV. A recently implemented model calibration methodology has been applied to determine the optimum set of resist model parameters. While the calibration is based on 1D (lines & spaces) patterns only, the model results are compared to 2D test structures for verification.