Dirk Killat

A Dual-Mode Single-Inductor Dual-Output Switching Converter With Small Ripple

Single-inductor dual-output (SIDO) switching converters always suffer from large ripple and severe cross-regulation problem, when a large inductor current is switched between two outputs. This paper proposes a novel fly capacitor method for SIDO converters to reduce the output ripple and spike. An adaptive common-mode control is presented to suppress the cross-regulation problem. A duty-ratio-based current estimation method is proposed to detect the load current, and the converter can automatically switch between pulsewidth modulation and pulse-frequency modulation modes. The two outputs of the converter are specified for 1.2 V/400 mA and 1.8 V/200 mA with input voltage ranging from 2.7 to 5 V. The chip has been fabricated on a 0.25-¿ m CMOS mixed-signal process. The conversion efficiency is 82% at a total output power of 840 mW, while the output ripple is about 20 mV and spike is less than 40 mV. The maximum overshot voltage during load response is 50 mV.

Measurement and modelling of sensitivity and noise of MOS magnetic field-effect transistors

Abstract The characteristics of magnetic field-sensitive split-drain MOSFETs (MAGFETs) have been experimentally measured. The sensitivity depends on the geometry and the operating point of the MAGFET. Particular attention is paid to the lateral parasitic conductance between the split drains. The equivalent spectral noise density of the magnetic flux density is measured. Additionally, a macro-model of the MAGFET has been developed for SPICE.

A 90% peak efficiency single-inductor dual-output buck-boost converter with extended-PWM control

Power management in portable devices demands small size, low cost as well as long battery lifetime, which in turn drive the development of single-inductor multiple-output (SIMO) converters [1–5]. Due to the battery voltage variation during usage and the wide-range dynamic voltage scaling (DVS) applied for power reduction, high-efficiency buck-boost conversion is required to extend the battery lifetime. The buck-boost converter in [6] selects the operation mode by comparing the output with the supply voltage, which is not suitable for multioutput converters. The reported single-inductor dual-output (SIDO) buck-boost converter in [4] uses a state machine with sophisticated current sense for mode selection and requires a freewheeling state that dissipates energy. The converter in [3] uses one additional auxiliary inductor for step-up/down mode adjustment. This paper proposes an extended-PWM (EPWM) control which automatically selects buck or boost mode and facilitates smooth mode transition. It is suitable for flexible outputs and maintains a high efficiency in buck and in boost converters.

A single-inductor dual-output switching converter with low ripples and improved cross regulation

This paper proposes a novel fly capacitor method for single-inductor dual-output (SIDO) switching converters to reduce the output ripples and spikes. An adaptive common-mode control is presented to suppress the cross regulation problem. The converter can automatically switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) control to improve the efficiency. The SIDO converter is specified for one channel 1.2 V/400 mA and the other 1.8 V/200 mA with input voltage ranging from 2.7 V to 5 V. The chip has been fabricated on a 0.25 μm CMOS mixed signal process. The conversion efficiency is 82% at a total output power of 840 mW while the output ripples are about 20 mV and spikes less than 40 mV.

Design of single-inductor dual-output switching converters with average current mode control

An average current mode controlled single-inductor dual-output (SIDO) buck converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. The proposed decoupling model helps to analyze the multi-loop system and to design the on-chip compensators. The converter has been fabricated in 0.25-mum mixed-signal process. Simulation and measurement results confirm the proposed analysis. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 KHz.

A single-inductor dual-output switching converter with average current mode control

An integrated single-inductor dual-output (SIDO) switching DC–DC converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. A decoupling small signal model is proposed to analyze the multi-loop system and to design the on-chip compensators. An average current control mode is introduced with lossless, continuous current detection. The converter has been fabricated in a 0.25 μm 2P4M CMOS process. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 kHz.

Signal processing for magnetic micro torque sensors

A novel type of signal processing for a magnetic micro torque sensor is described and simulated. The sensor principles are based on a soft magnetic core shaped as a yoke, two current-carrying coils, a soft magnetic amorphous ribbon with strong magnetostrictive properties that is fixed on a shaft, and at least two magnetic flux-density sensors. The sensor determines directly the change of permeability of the amorphous ribbon on the shaft. Nevertheless, the variation of the air gap between the sensor and the rotating shaft affects the measurement principle. Therefore, the magnetic flux density is measured at two positions, one at the face of the soft magnetic core and the other beside the face of the core in the area of the stray flux. The evaluation of these two flux densities yields the distance between the sensor and the shaft as well as the permeability of the amorphous ribbon. The problem arising with this practice is the determination of the sensitivity of the flux-density sensors. As the current-carrying coils are alternately operated in a common and a push-pull mode, the unknown sensitivities of the flux-density sensors do not affect the evaluation of the permeability of the amorphous ribbon on the shaft.

Phased array transducer for emitting 40-kHz air-coupled ultrasound without grating lobes

We introduce an ultrasonic one-dimensional (1D) air-coupled phased array transducer, operating at 40 kHz without any grating lobes. It is well known, that this achievement is only possible when each transducer element is small enough for an element pitch that is equal to or less than half of the wavelength, i.e. ≤ 4.3 mm for 40 kHz operation frequency. As far as we know, conventionally low frequency array designs for air-coupled transducer applications were not possible at 40 kHz due to this inter element spacing requirement. The main idea is to separate the acoustic aperture from the actual radiating aperture of the ultrasonic transducer. We use acoustic waveguides, forming a smart packaging layer, to fulfill the half-wavelength criteria for the pitch and to benefit from concentrating the acoustic energy from several single ultrasonic transducers into a smaller effective aperture. A proof-of-concept prototype array was built and characterized. An impressive 130 ± 1 dB sound pressure level (SPL) is observed at a distance of 1 m. The opening angle of the array is 110° in total, without any grating lobes. For future work, we plan extending the approach to build an air-coupled fully populated 2D phased array transducer as well.

Technique for reducing on-resistance of high-voltage drivers based on stacked standard CMOS

This paper presents a new technique for reducing on-resistance of high-voltage drivers, which are based on N-stacked standard CMOS. A theory to calculate gate voltages of HV-driver transistors to drive the maximum drain current for minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology for generating them is described. This concept is technology independent and compatible with scaled CMOS devices. The theory and circuit design are proved by simulating a 2-stack CMOS driver in 65-nm technology, demonstrating significantly improved rise and fall times of the driver, if compared to previous work.

An experimental extracted model for latchup analysis in CMOS process

The latchup phenomenon is analyzed theoretically. A practical analytical model derived from Ebers-Moll formulations is proposed to analyze, simulate, and predict latchup, with favorable legitimacy and flexibility. The model parameters are extracted on 0.25um CMOS process from experiments. The extracted model can predict latchup successfully in circuit level when applied in SPICE1.