Hongcheng Xu

A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants

This paper presents an integrated neural stimulator with highly efficient and flexible frontend which is intended for an epiretinal implant with 1024 electrodes. It features programmable stimulation pulse shapes, a high-voltage (HV) output driver with compliance monitor for supply voltage adaptation, active and passive charge balancers, and electrode impedance measurement. Area and power efficiency is achieved by global timing assignment and local amplitude control over a bus at the local stimulation units. Major power savings in the distributed digital control units are realized by implementing global and local clock gating. Two stimulator frontends have been fabricated in a 0.35 μm HVCMOS process. Each frontend features four demultiplexed outputs and consumes 0.2 mm2 core area. A maximum voltage compliance of 20 V is achieved and up to 1 mA of output current can be adjusted with up to 50 dB dynamic range. In vitro experimental results performed on a platinum black electrode in 0.9% saline solution are given.

A Temperature and Process Compensated Ultralow-Voltage Rectifier in Standard Threshold CMOS for Energy-Harvesting Applications

This brief presents an ultralow-voltage multistage rectifier built with standard threshold CMOS for energy-harvesting applications. A threshold-compensated diode (TCD) is developed to minimize the forward voltage drop while maintaining low reverse leakage flow. In addition, an interstage compensation scheme is proposed that enables efficient power conversion at input amplitudes below the diode threshold. The new rectifier also features an inherent temperature and process compensation mechanism, which is achieved by precisely tracking the diode threshold by an auxiliary dummy. Although the design is optimized for an ac input at 13.56 MHz, the presented enhancement techniques are also applicable for low- or ultrahigh-frequency energy scavengers. The rectifier prototype is fabricated in a 0.35-μm four-metal two-poly standard CMOS process with the worst-case threshold voltage of 600 mV/- 780 mV for nMOS/pMOS, respectively. With a 13.56 MHz input of a 500 mV amplitude, the rectifier is able to deliver more than 35 μW at 2.5 V VDD, and the measured deviation in the output voltage is as low as 180 mV over 100°C for a cascade of ten TCDs.

An AC-powered optical receiver consuming 270μW for transcutaneous 2Mb/s data transfer

Improving communication with implantable systems remains an important topic of research due to the limitations in power dissipation and the simultaneous need for high data rates. Neural recorders generate well above 10Mb/s data [1], which needs to be transmitted out-of-body. Multichannel stimulators, such as epiretinal implants, need control data in the range of several Mb/s for the into-body link [2]. Up to now, RF has been the dominant form of transcutaneous communication. One major issue is the crosstalk between the RF power link and the data signal. Therefore, dual-band telemetry is common in order to spectrally separate the data and power transfer. The standards reach from UWB transmitters [1], MICS band [3], to customized [2] RF receivers, often using sophisticated digital encoding. Also, orthogonal alignment has been used for the data and power coils to suppress crosstalk. Such RF communication needs a 2nd pair of coils, and the state-of-the-art power consumption ranges from 1.5 to 3nJ/b at rates of 120kb/s to 2.5Mb/s [3].

A multichannel neurostimulator with transcutaneous closed-loop power control and self-adaptive supply

This paper presents an integrated multichannel neurostimulator ASIC with improved power management efficiency. The stimulator features transcutaneous closed-loop power control that enables optimum power transfer in spite of the coupling variation as well as the variation in the stimulation threshold/current. A programmable adaptive supply in the high voltage (HV) domain is further proposed to minimize the power dissipation during the active stimulation mode in terms of stimulus current/electrode impedance inconsistencies. The stimulator prototype, including the power management, the digital control as well as a 16 channel stimulation frontend, is fabricated in AMS 0.35μm HV CMOS technology. In measurements, automatic supply voltage adaptation from 13.1V to 8V with running stimulations has been achieved, resulting in maximum power saving of 40% for the implantable circuit.

A bidirectional neural interface with a HV stimulator and a LV neural amplifier

This paper shows a neural stimulator with 15V supply voltage combined with a neural low-noise amplifier (LNA) with a supply of ±1.65V around the common mode voltage (VCM) of 7.5V. In most implementations, the stimulator and recorder use the same supply domain, thus either leading to low voltage compliance (VC) for the stimulator or to high power consumption in the recorder. Obviously, a separation of both is the preferable choice, but comes with the challenge of effective protection of the low voltage (LV) sensitive input nodes of the recorder. A high voltage (HV) transistor used as a switch between the two parts enables different supply voltages for stimulator and recorder. Thus, a high current stimulator with high VC can be combined with a high efficient LV neural recorder. The presented implementation shows a stimulator with a maximum stimulation current of ±15mA with 5-bit resolution out of a 15V supply. The recording part consists of a LNA with a VCM of 7.5V and a supply voltage of ±1.65V around VCM - VDDLNA=9.15V and VSSLNA=5.85V. It consumes only 11.8μW and achieves an input referred root-mean-square (RMS) noise of 5.5μV in the frequency band of 1Hz to 100kHz. The design is implemented and simulated in a 0.18μm HV technology.

A new class of integrated CMOS rectifiers with improved PVT-compensated efficiency

We review in this paper a new class of integrated CMOS rectifiers with improved PVT-compensated efficiency and propose also a new voltage quadrupler. By utilizing a threshold compensation technique, the presented circuits are able to achieve both high voltage conversion efficiency (VCE) and power conversion efficiency (PCE) with only standard threshold devices at low input amplitudes. Besides, the performance of the rectifiers is selfcompensated over process and temperature, which is achieved by precisely tracking the diode threshold drift with an auxiliary dummy. The rectifiers are implemented in AMS 0.35μm 4M/2P standard CMOS process and the simulated performance is shown at an input frequency of 13.56MHz. For the proposed voltage quadrupler, at 0.8V input amplitude and 2kΩ load resistor, output voltage of 1.52V can be achieved with VCE and PCE of 48% and 49%, respectively. As compared to previously published results, the improvement is up to 358% in VCE and 351% in PCE. Besides, the maximum deviation in its output voltage is as low as 162mV over 100°C temperature span, which outperforms the conventional structure by almost an order of magnitude.

Wide-band wide-input efficiency-enhanced CMOS rectifier with self temperature and process compensation

We present in this paper the design of a wide-band wide-input efficiency-enhanced CMOS rectifier for inductively powered telemetric systems. The integrated gate controlled diode is developed for the rectifier to minimize the dropout voltage in the forward conducting path, while maintaining low reverse leakage flow. Besides, the new rectifier features an implicit temperature and process compensation mechanism, that effectively reduces the deviation in the output voltage by tracking the threshold drift in the main diode device. The rectifier is optimized for high output power in this design, but the technique can be easily implemented for micro energy harvesters where the input voltage/power is low. The rectifier is fabricated in AMS 0.35µm 4M/2P standard CMOS process with maximum threshold of ∣VTHP∣=1.12V and VTHN=0.8V. With a 13.56MHz input at 5V amplitude and a load resistor of 1.8k, the rectifier achieves 84.4% voltage conversion efficiency and 82% power conversion efficiency. The performance remains essentially unchanged from 1MHz to 20MHz input frequency and slight variation from 1.5V to 5.5V input amplitude.

Technique for reducing on-resistance of high-voltage drivers based on stacked standard CMOS

This paper presents a new technique for reducing on-resistance of high-voltage drivers, which are based on N-stacked standard CMOS. A theory to calculate gate voltages of HV-driver transistors to drive the maximum drain current for minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology for generating them is described. This concept is technology independent and compatible with scaled CMOS devices. The theory and circuit design are proved by simulating a 2-stack CMOS driver in 65-nm technology, demonstrating significantly improved rise and fall times of the driver, if compared to previous work.

Wide-band efficiency-enhanced CMOS rectifier

We present in this paper the design of a wide-band efficiency-enhanced CMOS rectifier. A novel semi-active diode is proposed to minimize both the diode forward voltage drop and the reverse leakage current. This is achieved by dynamically configuring the rectification device as a threshold compensated diode in the on-state while a standard MOS diode in the offstate, respectively. The proposed rectifier is implemented in a 0.35μm 4M/2P standard CMOS process. In simulation, with 5.5V AC input at 13.56MHz, the rectifier outputs 4.94V DC voltage across a 1.2kΩ load resistor, achieving 87% power conversion efficiency (PCE) and 90% voltage conversion efficiency (VCE). The PCE and VCE can be maintained from 1MHz to 20MHz input frequency, with only 3% deviation in the PCE and 2% deviation in the VCE. In addition, the performance of the rectifier is self-compensated over temperature and process. From -40°C to +130°C, the simulated VCE varies within 2% from 89.6% to 87.7%, while the PCE stays almost constant at 86%. With 200 Monte Carlo samples, the standard deviation in the PCE and VCE are as low as 0.56% and 0.57%, respectively.

Design of high speed high-voltage drivers based on stacked standard CMOS for various supply voltages

This paper presents a new concept for reducing on-resistance of high-voltage drivers based on stacked MOSFETs for various supply voltages. A theory to calculate gate voltages of an N-stacked CMOS driver to drive the maximum drain current at a minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology is described to generate them. The principle is applied on a 2-stack CMOS driver in 65-nm with a nominal voltage of the I/O-devices of 2.5 V. For various supply voltages, simulations show an improvement of 27%-86% reduction of the initial on-resistance and approximately 16%-83% improved rise and fall times of the output signal at a load capacitance of 150 pF if compared to previous work. The principle can be applied to N-stack driver transistors.