Sara Pashmineh

Technique for reducing on-resistance of high-voltage drivers based on stacked standard CMOS

This paper presents a new technique for reducing on-resistance of high-voltage drivers, which are based on N-stacked standard CMOS. A theory to calculate gate voltages of HV-driver transistors to drive the maximum drain current for minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology for generating them is described. This concept is technology independent and compatible with scaled CMOS devices. The theory and circuit design are proved by simulating a 2-stack CMOS driver in 65-nm technology, demonstrating significantly improved rise and fall times of the driver, if compared to previous work.

Design of high speed high-voltage drivers based on stacked standard CMOS for various supply voltages

This paper presents a new concept for reducing on-resistance of high-voltage drivers based on stacked MOSFETs for various supply voltages. A theory to calculate gate voltages of an N-stacked CMOS driver to drive the maximum drain current at a minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology is described to generate them. The principle is applied on a 2-stack CMOS driver in 65-nm with a nominal voltage of the I/O-devices of 2.5 V. For various supply voltages, simulations show an improvement of 27%-86% reduction of the initial on-resistance and approximately 16%-83% improved rise and fall times of the output signal at a load capacitance of 150 pF if compared to previous work. The principle can be applied to N-stack driver transistors.

Self-biasing high-voltage driver based on standard CMOS with an adapted level shifter for a wide range of supply voltages

This paper presents the design of a high-voltage driver based on stacked standard low-voltage CMOS with an adapted level shifter. Both circuits are designed in 65-nm TSMC technology with a nominal voltage of 2.5 V without any passive elements. The control voltages to regulate the stacked transistors of the HV-driver are achieved by proposing cascode self-biasing method, therefore no reference voltages are required. The driver and the level shifter are optimized for arbitrary supply voltages from 3.5 V to 7.5 V. This range is extended by 66.7% when compared against common drivers and level shifters being suitable for a supply voltage range of 2.4 V between 5.1 V and 7.5 V. The circuit is stable for temperatures between -45 °C and 125 °C , and has no overvoltage between the terminals of each transistor.

Current Feedback Linearization Applied to Oscillator Based ADCs

A regulation scheme to linearize the tuning curve of CMOS ring oscillators is proposed in this paper. The scheme uses the current consumption of the CMOS ring elements, which is proportional to the output frequency to the first order. The design of the feedback loop is presented on system level in conjunction with performance enhancements made on the implementation level. A weakly non-linear ring oscillator model is developed to simplify the control loop design. Model based linearity simulations proof a good agreement with measurements, while the simulation time is significantly reduced. A proof of concept implementation of the proposed linearization technique using CMOS ring oscillators is presented. Operating at 50 MHz sampling frequency, a maximum SFDR of 83.8 dB in a narrow band configuration verifies the effectiveness of the linearization. Implemented in a 180 nm process, the active area of the circuit is only 0.03 mm2, which enables the use of this technique for multi-channel, multi-parameter measurement applications.

An LDO using stacked transistors on 65 nm CMOS

This paper presents a low drop-out voltage regulator (LDO) suitable for input voltages twice the nominal operating voltage of the CMOS technology. High GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. Two feedback loops are used to improve stability. High voltage compatibility is established by stacking two pass transistors. The first pass transistor is controlled by the main error amplifier; the 2nd pass transistor is controlled by 2nd amplifier adjusting the division of the voltages between the two pass transistors. The paper presents circuit design and simulations results of a LDO with 500 mA output current using the 2.5 V transistors of the TSMC 65 nm CMOS low-power process technology.

Design of a high-voltage rail-to-rail error amplifier based on standard CMOS used in an LDO

This paper presents the design of a high-voltage (HV) rail-to-rail error amplifier. This circuit controls the output signal of a low drop-out voltage regulator (LDO) according to the reference voltages and based on stacked standard transistors. The circuit is designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and is optimized for arbitrary values of supply voltage up to 5.0 V. The error amplifier consists of 3 stages and 2 feedback loops. The stages are internally connected rail-to-rail to achieve high GBW and DC accuracy. The simulation and measurement results for the designed HV-error amplifier show that the output signal of the LDO tracks the reference voltages. The circuit design is technology-independent and compatible with scaled CMOS.

A high-voltage driver based on stacked low-voltage transistors with minimized on-resistance for a buck converter in 65 nm CMOS

This paper presents a high-voltage (HV) driver for switching a buck converter. The circuit is based on 3-stacked CMOS using gate control circuits to drive maximum current which indicates minimized on-resistance of the HV-driver thus achieving faster switching. The circuit is designed and fabricated using 65 nm CMOS TSMC process technology with a nominal voltage of 2.5 V and with a supply voltage of 5.5 V. Since the design is based on stacked CMOS transistors, the circuit is technology-independent. The initial on-resistances of the driver pull-up and the pull-down paths have an improvement of 75% and 36% respectively. Due to a buck converter switched by the designed HV-driver, output voltages in the range of 0.45 V to 2.45 V can be achieved from different high supply voltages in the range of 3.5 V to 5.5 V. The circuit occupies an area of 0.187 mm2.

Design of High-Voltage Level Shifters Based on Stacked Standard Transistors for a Wide Range of Supply Voltages

This paper presents the design of two high-voltage level shifters suitable for a wide range of supply voltages. In view of certain drawbacks identified during the design, implementation, simulation and measurement of a 3-stacked CMOS driver using capacitive feedback level shifters, improved high-voltage level shifters are designed. These circuits are compared with each other in terms of their circuit description, drawbacks, advantages and simulation results. The circuit designs are technology-independent and compatible with scaled CMOS devices because these circuits are based on stacked standard transistors. Both high-voltage level shifters are proved by simulating in 65-nm TSMC technology with a nominal voltage of 2.5 V. The level shifter can be applied for supply voltages between 2.6 V / 3.5 V and 7.5 V, respectively. The supply voltage range is extended by 67% and 104% respectively when compared against common level shifters.

Design of a high-voltage differential amplifier based on stacked low-voltage standard CMOS with different input stages

This paper presents the design of a high-voltage differential amplifier using six different pre-input stage circuits to reduce high-voltage input levels to low-voltage signals. The proposed circuits are designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and a supply voltage of 5 V. The designs are based on stacked low-voltage standard CMOS transistors. The different pre-input stage circuits are compared to each other in terms of their circuit description, drawbacks, advantages and simulation results. The principle of the five designed pre-input stage circuits can be applied to higher voltage range input signals as well.

Design of a high-voltage driver based on low-voltage CMOS with an adapted level shifter optimized for a wide range of supply voltage

This paper presents the design of a high-voltage driver with an adapted level shifter for switching converters. The proposed HV-driver and level shifter are based on stacked standard CMOS, therefore the design is technology independent. The circuit is designed in 65-nm TSMC technology with a nominal voltage of 2.5 V and optimized for arbitrary supply voltages from 2.6 V to 6.0 V. This range is extended by 41.7% when compared against common drivers and level shifters with the circuit being suitable for a supply voltage range of 2.4 V between 2.6 V and 5.0 V. The total area of the designed level shifter is about 3.8% of that required for similar circuit in previous work.