Dirk Leipold

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed /spl Sigma//spl Delta/ dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13-/spl mu/m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is -112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below -62 dBc, while the far-out spurs are below -80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

A first multigigahertz digitally controlled oscillator for wireless applications

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering, yet the resulting spurious tones are very low. This enables to employ fully digital frequency synthesizers in the most advanced deep-submicrometer digital CMOS processes, which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a digital signal processor to investigate noise coupling. The 2.4 GHz DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of -110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates

Digital RF processing: toward low-cost reconfigurable radios

RF circuits for multi-gigahertz frequencies have recently migrated to state-of-the-art low-cost digital CMOS processes. This article visits fundamental techniques recently developed that migrate RF and analog design complexity to the digital domain for a wireless RF transceiver. All-digital phase locked loop and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software-defined radio. The ideas presented have been used to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS

An all-digital frequency synthesizer for a single-chip Bluetooth radio is fabricated in 0.13/spl mu/m CMOS, and operates in a digitally-synchronous phase domain that naturally incorporates wideband GFSK modulation. The synthesizer includes a pulse-shaping TX filter and near class-E PA with digital amplitude control. Close-in phase noise is -86.2dBc/Hz, integrated rms phase noise is 0.9/spl deg/, and settling time is /spl les/ 50/spl mu/s.

A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS

We present the first 90-nm digital CMOS RF power amplifier. This PA contains a large array of NMOS switches, and performs a direct digital-to-RF-amplitude conversion, filtering and buffering in a fully-integrated GSM/EDGE transmitter. Power control is fully digital. 40% efficiency is obtained at 10-dBm output power from 1.4 V and it occupies 0.005 mm/sup 2/.