Meng-Chang Lee

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of -110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates

A digitally controlled oscillator system for SAW-less transmitters in cellular handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.

A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process

We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive chain uses discrete-time analog signal processing to down convert, down- sample, filter and analog-to-digital convert the received signal. An auxiliary feedback is provided at the mixer output that can linearize the entire receive chain. The receiver meets a sensitivity of -110 dBm at 60 mA in a 1.4V digital CMOS process

A first RF digitally-controlled oscillator for mobile phones

We propose and demonstrate the first RF digitally-controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip fully-compliant quad-band GSM transceiver realized in a 90 nm digital CMOS process. Frequency tuning is achieved through digital control of an array of standard n-poly/n-well MOSCAP devices. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. We analyze the effect of high-speed varactor dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the dithering.

A first RF digitally-controlled oscillator for SAW-less TX in cellular systems

A first digitally-controlled oscillator for mobile stations is presented. Combining a MTM capacitor and two NMOS transistor arrays for the varactor as an RF DAC, a highly linear oscillator gain is achieved, and is insensitive to process shift. With a sigma-delta dithering, a fine frequency resolution is obtained while having negligible phase noise degradation. The measured -167dBc/Hz at 20MHz offset from 915MHz carrier proves that this DCO system can be used in a SAWless transmitter for mobile phones.

An ultra low phase noise GSM local oscillator in a 0.09 /spl mu/m standard digital CMOS process with no high-Q inductors

A design approach is presented for realizing a fully integrated local oscillator, covering all 4 GSM bands, and fulfilling the stringent phase noise requirement of -162 dBc/Hz at a 20-MHz offset from a 915-MHz carrier in a 1.4-V 0.09-/spl mu/m digital CMOS process. By operating a digitally-controlled oscillator at a 4/spl times/ frequency followed by /spl divide/ 4 frequency dividers, the requirements of on-chip inductor Q and the amount of gate oxide stress are relaxed. Both dynamic and SCL dividers are also studied for their phase noise performance. It was found that a dynamic divider is needed for stringent TX outputs while an SCL divider can be used for RX to save power. Both dividers are capable of producing a tight relation between 4 quadrature output phases at low voltage and low power.