Roman Staszewski

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of -110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates

A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process

We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive chain uses discrete-time analog signal processing to down convert, down- sample, filter and analog-to-digital convert the received signal. An auxiliary feedback is provided at the mixer output that can linearize the entire receive chain. The receiver meets a sensitivity of -110 dBm at 60 mA in a 1.4V digital CMOS process

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.

Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver as implemented in the first single-chip GSM radio in 90 nm CMOS. It demonstrates benefits of using programmable digital control logic in deep-submicron CMOS RF system. It also describes a micro-processor architecture design in digital RF processor (DRP) and how it controls compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance

A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS

In this paper we present a quad-band single-chip GSM/GPRS radio in 90nm digital CMOS process based on the Digital RF Processor (DRP™) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging amplitude and phase information directly in an RF DAC. The receiver is based on direct RF sampling and discrete-time analog signal processing. A dedicated internal microprocessor manages the digital RF controls to provide best achievable RF performances. The transceiver exceeds all 3GPP specifications demonstrating a receive NF of 1.8 dB and a margin of 8dB on TX spectral mask at 400 KHz offset in GSM850/900 bands. The transceiver is best-in-class in area and occupies only 3.8 mm2 of silicon area.