Divya Pathak

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling

Heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. In this paper, an ElasticCore platform is described where core resources along with the operating voltage and frequency settings are scaled to match the application behavior at run-time. Furthermore, a linear regression model for power and performance prediction is used to guide the scaling of the core size and the operating voltage and frequency to maximize efficiency. Circuit considerations that further optimize the power efficiency of ElasticCore are also considered. Specifically, the efficiency of both off-chip and on-chip voltage regulators is analyzed for the heterogeneous architecture where the required load current changes dynamically at run-time. A distributed on-chip voltage regulator topology is proposed to accommodate the heterogeneous nature of the ElasticCore. The results indicate that ElasticCore on average achieves close to a 96% efficiency as compared to an architecture implementing the Oracle predictor where the application behavior is perfectly matched at run-time. Moreover, the proposed architecture is 30% more energy-efficient as compared to the BigLitte architecture.

Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping

In the recent years, many-core platforms have emerged to boost performance while meeting tight power constraints. Per-core Dynamic Voltage and Frequency Scaling (DVFS) maximizes energy savings and meets the performance requirements of a given workload. Given a limited number of I/O pins and the need for finer control of voltage and frequency settings per core, there is a substantial cost in using off-chip voltage regulators. Consequently, there has been increased attention on the use of on-chip voltage regulators (OCVR) in many-core systems. However, integrating OCVRs comes at a cost of reduced power conversion efficiency (PCE) and increased complexity in the power delivery network and management of the OCVRs. In this paper, the effect of PCE on the thread-to-core mapping algorithm is investigated and the importance of the PCE-aware mapping scheme to optimize energy-efficiency is highlighted. Based on the results, up to 38% more energy savings is achieved as compared to PCE-agnostic algorithms. Moreover, the impact of core clustering granularity and process variation on the total efficiency of the system is explored. When relaxing the energy constraints by just 10%, an effective mapping reduces the complexity of the power delivery system by allowing the use of a significantly smaller number of voltage regulators, as compared to per-core OCVR. The results provided in the paper indicate an important opportunity for system and circuit co-design to implement energy-efficient and complexity-effective platforms for a target workload.

Energy efficient on-chip power delivery with run-time voltage regulator clustering

In this paper, a power delivery system for homogeneous chip multi-processor (CMP) systems is proposed. The power delivery system is modified at run time by clustering multiple on-chip voltage regulators (OCVR) depending on the power demand of the workload. The OCVRs are designed to deliver up to the average current requirement of the typical workloads executed on the CMP platform. When the current demand of a core cluster exceeds the average value, the output of multiple OCVRs is combined through a high-speed s witch network to provide the necessary current. Two OCVR topologies (Buck and LDO) are analyzed to characterize the impact on the characteristics of the voltage regulator as the peak load current is reduced. Simulation results for run-time OCVR clustering indicate a 36% reduction in the energy consumption of the system at an average load current with improvement in the load regulation. In addition, the area occupied by the OCVRs is reduced by at least 70%.

26.2 Power supply noise in a 22nm z13™ microprocessor

Successful power supply noise mitigation requires a system-level approach that includes design and modeling of the mitigation circuits with the power delivery network (PDN) on the chip, the chip module, the backplane, and the voltage regulator module (VRM). Traditionally, periodic square-wave activity patterns with all cores in sync, which yield low-frequency (LF) or mid-frequency (MF) impedance peaks associated with the backplane and chip/module, respectively, are considered to give rise to the worst case power supply noise. However, voltage droops that are both deeper and faster at a single victim core are created when cores change activity in more complicated patterns, termed as perfect storms in this work. These patterns excite high-frequency (HF) modes that are not stimulated when all cores switch simultaneously, and require an accurate model of the packaged chip, including effective core-to-core inductances due to currents traveling between cores through low-resistance module planes.

Load Balanced On-Chip Power Delivery for Average Current Demand

A dynamic power management system for homogeneous chip multi-processors (CMP) is proposed. Each core of the CMP includes on chip DC-DC switching buck converters that are interconnected through a switch network. The peak current rating of the buck converter is selected to meet only the average current demand of the load circuit. A real-time load balancing algorithm is developed which reconfigures the power delivery network by combining the output of multiple buck converters when the workload demand exceeds the peak current rating. Simulation results for the proposed power delivery method indicate up to a 44% reduction in the energy consumption of the CMP system. In addition, the on-chip footprint of the power delivery network, including the on-chip voltage regulators and the switching network, is reduced by at least 23%.

Run-time voltage detection circuit for 3-D IC power delivery

An advantage of 3-D integrated circuits is the possibility to integrate heterogeneous technologies on separate device planes. The device planes are fabricated in different technologies operating at distinct power supply voltages. A mechanism to detect and set the power supply voltage of each domain within each device plane of a 3-D IC is described. The detection of the power supply voltage is achieved through the placement of a ring oscillator circuit in each voltage domain. The current is supplied at the set voltage to the device plane through dedicated power modules comprising of a frequency to voltage converter and a dependent voltage source placed on a dedicated power plane. The functionality of the supply voltage detection and delivery circuits is verified through SPICE simulation of the device plane (22 nm technology) and power plane (45 nm technology). The implementation of the proposed circuits for 3-D IC design facilitate a plug-and-play approach for the integration of heterogeneous technologies.

Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery

An energy efficient power delivery method for multi-core systems with under-provisioned on-chip voltage regulators has been proposed in literature. The power delivery network is reconfigurable at run-time to meet the varying current demands of the cores exceeding the maximum output current rating of the voltage regulators. In this paper, a real-timeworkload scheduling heuristic is developed that assigns the tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators. The work load scheduler is evaluated on homogeneous and heterogeneous multi-core platforms based on the Exynos 5410 big.LITTLE architecture. The proposed workload scheduler along with the run time voltage regulator clustering algorithm proposed in the literature provides a robust cross-layer power management technique for under-provisioned on-chip power delivery.

Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery

In this paper, a dynamic on-chip power delivery system for chip multiprocessors (CMPs) is proposed, analogous to the smart grid deployed for large-scale energy distribution. The system includes underprovisioned on-chip voltage regulators (VRs) interconnected through a switch network. The peak current rating of the VRs is selected to meet only the average current demand of the cores. A real-time load-balancing algorithm is developed to reconfigure the power delivery network (PDN) by combining the output of multiple VRs when the workload demand exceeds the peak current rating of a single regulator. An operating system level task scheduling heuristic distributes the workloads on the cores such that the required reconfiguration of the PDN is minimized. Simulation results for the proposed power delivery system indicate up to a 44% reduction in the energy consumption of the CMP. In addition, the on-chip footprint of the PDN, including the on-chip VRs and the switching network, is reduced by at least 23%. The proposed cross-layer power management technique is an optimum solution for power-constrained many-core architectures implemented in advanced technology nodes.

Power supply voltage detection and clamping circuit for 3-D integrated circuits

A circuit that detects and sets the power supply voltage of a given device plane in a 3-D IC is proposed. The circuit consists of 1) a ring oscillator in each voltage domain located in each device plane, and 2) a power module placed in a dedicated power plane. The power module consists of four components; a divide-by-40 clock divider, a frequency detector, a voltage ramp generator, and a voltage peak detector circuit. The power module provides a stable reference voltage equal to the power supply voltage of the targeted voltage domain in the device plane. SPICE simulations of the circuit indicate that power supply voltages of less than 1 V are successfully set and provided as a reference to an on-chip voltage regulator within 500 ns and with reference voltage variation of less than 1%. The power module is integrated with on-chip voltage regulators which require a precise voltage reference. The proposed implementation permits dynamic voltage and frequency scaling and point of load power delivery.