Divya Vijayaraghavan

Multi-protocol embedded PCS IP in a FPGA-SOC

Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbps data rates. Ensuring quality meant adopting a strongly modular approach to design and verification. The configuration space of the Hard IP had to be bounded intelligently. Major architectural enhancements were necessary instead of a simple performance upgrade of the previous Hard IP. Verification complexity mandated design and verification re-use. Emulation and vendor soft IF interoperability testing was another strategy employed for first silicon success

Packet arrival time in 1588 for 40GE/100GE

1588 timestamping assumes a well-defined instant at which the beginning of a packet crosses the reference plane between the precision time protocol (PTP) node and the network. However, this definition is not clear in the case of a multi-lane serial bus such as 40GE/100GE. Furthermore, there is an implied time-ordering between the lanes of a serial bus that is not captured in the existing definition. This paper explores issues with multi-lane serial buses as it relates to time-stamping and proposes revised definitions for packet arrival time in the case of a serial bus.