Doede Terpstra

Selective-epitaxial base technology with 14 ps ECL-gate delay, for low power wide-band communication systems

A silicon bipolar technology is presented that incorporates a selectively epitaxially grown base in a double-polysilicon transistor. Si-bases as well as Si-SiGe-multilayer bases are applied. Both result in excellent device performance, with cut-off and maximum oscillation frequencies up to 45 GHz, and ECL-gate delays down to 13.7 ps. DC-coupled broad-band amplifiers for 15 Gbit/s optical data links have been fabricated, providing record bandwidths of 13.2 GHz. As selective epitaxial growth is performed at 700/spl deg/C in a production epitaxial reactor, this technology can easily be combined with current semiconductor manufacturing technology.

Explorations for high performance SiGe-heterojunction bipolar transistor integration

Presents a SiGe HBT integration-study, introducing a low-complexity integration-scheme. We demonstrate a stepped box-like SiGe base-profile designed to reduce reverse Early effects, achieving f/sub T/=55 GHz and BV/sub CEO/=2.7 V. The transistor characteristics are well modeled by Mextram 504.

Selective versus non-selective growth of Si and SiGe

Selective epitaxial growth of Si and SiGe at low temperatures and reduced pressure in a single-wafer CVD reactor has been characterized with respect to its sensitivity to pattern changes. Small variations in the surface ratio of nitride (or oxide) and exposed Si cause relatively large deviations in the growth rates. The Si and SiGe growth rates are affected in opposite ways. Even worse are pattern discontinuities across the area to be deposited, unavoidable at the edge of the wafer. These discontinuities are detrimental to the deposition uniformity and are active over a long range. A sacrificial poly layer has been successfully applied to overcome these problems. An alternative solution is the deposition of a continuous Si layer which grows epitaxially on the Si in the windows and polycrystalline on the nitride or oxide fields. This offers the same advantages in suppressing the loading effects, albeit that the specific features of selective growth are lost. A limited comparison of the two growing methods in terms of process robustness was made. There is no clear winner, each method has its own share of problems.

High-performance SiSiGe HBTs SiGe-technology development in Esprit Project 8001 TIBIA: An overview

Abstract Five major European Semiconductor Companies have cooperated on the development of technologies for the fabrication of Si SiGe-based Heterojunction Bipolar Transistors. This cooperation was part of the European Community Esprit Project 8001 TIBIA, on BICMOS Technology Development and Applications. This article presents an overview of the various concepts studied by the projet-partners, the fabrication processes and the results obtained on single devices and preliminary test-circuits (which already demonstrate the added value of Si SiGe HBTs in existing Si-technology). A more detailed description is given of the process studied at Philips, which involves double-polysilicon transistors with a selectively deposited Si SiGe base.

Loading Effects During Low-Temperature Seg Of Si And SiGe

Selective Epitaxial Growth (SEG) of Si and SiGe suffers from pattern sensitivity. The growth rate and layer composition change with the pattern and the window size. In relation to growth at atmospheric pressure, the sensitivity to the window size is suppressed at reduced pressure, whereas some growth rate effects of a more global nature become more visible. The Si growth rate decreases when the area of exposed silicon on the wafer and the susceptor decreases. SiGe shows the opposite behavior: its growth rate increases with decreasing silicon area. Another difference between Si and SiGe is the range over which the loading effects are active. The influence of a large silicon area on the Si growth rate can be felt inches away, whereas the SiGe growth rate is affected over a much shorter distance. In common epi reactors the wafer rests on a susceptor, which extends beyond the wafer, exposing a large Si-coated surface area around the circumference of the wafer. Consequently, the Si growth rate varies unacceptably across the wafer. A sacrificial polysilicon layer has been successfully applied to improve the growth rate uniformity across the wafer.