Domagoj Siprak

Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices

This paper deals with the design of single-stage differential low-noise amplifiers for ultra-wideband (UWB) applications, comparing state-of-the-art planar bulk and silicon-on-insulator (SOI) FinFET CMOS technologies featuring 45-nm gate length. To ensure a broadband input impedance matching, the g m-boosted topology has been chosen. Furthermore, the amplifiers have been designed to work over the whole UWB band (3.1-10.6 GHz), while driving a capacitive load, which is a realistic assumption for direct conversion receivers where the amplifier directly drives a mixer. The simulations (based on compact models obtained from preliminary measurements) highlight that, at the present stage of the technology development, the planar version of the circuit appears to outperform the FinFET one. The main reason is the superior cutoff frequency of planar devices in the inversion region, which allows the achievement of noise figure and voltage gain comparable to the FinFET counterpart, with a smaller power consumption.

Reduction of RTS Noise in Small-Area MOSFETs Under Switched Bias Conditions and Forward Substrate Bias

Low-frequency noise in small-area MOSFETs is dominated by random telegraph signal noise associated to the capture and emission of charge carriers by a single trap located in the gate dielectric. RTS noise degrades the performance of analog, digital, and memory circuits. In this paper, we present measurements and simulations of RTS noise in small-area MOSFETs under constant bias and switched gate bias conditions in order to investigate the impact of substrate bias on RTS noise. Our results show that a strong reduction of RTS noise under switching bias conditions is obtained when a forward substrate bias is applied during the device off-state. Measurement of RTS mean emission and capture times proves that such a reduction of RTS noise is caused by a significant decrease in emission time constant occurring when a low gate voltage and a positive substrate voltage are simultaneously applied in the frame of a switching bias scheme.

Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias

A new concept of noise reduction in CMOS circuits is presented taking advantage of a strong reduction of MOSFET low-frequency noise occurring under switched gate bias conditions and forward substrate bias. The effect of forward substrate bias on noise reduction is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. A bias scheme adopting forward substrate bias only during the transistor off-state is suggested by the measurement results of transconductance efficiency gm/Id and intrinsic voltage gain gm/gds showing that these figures of merit are degraded when a forward substrate bias is applied during the on-state. As a first example exploiting the found noise reduction on circuit level, a 14 GHz pMOS VCO is presented. Our results show a significant reduction of close to carrier phase noise when a forward substrate bias is applied to the MOSFETs providing the negative conductance stage for the oscillation of the VCO. The outlined principles can be extended to other circuits and motivate new topologies and biasing schemes for analog and radio frequency CMOS circuits.

Measurement and simulation of gate voltage dependence of RTS emission and capture time constants in MOSFETs

Random telegraph signal (RTS) affecting the drain current of small area n-type MOSFETs is extensively investigated. We report measurements and simulations of emission (Tc) and capture (Tc) time constants as a function of gate voltage for several individual traps. Different models proposed in the literature are applied and compared.

Self Heating Simulation of Multi-Gate FETs

Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. This work demonstrates a simplification of the approach to a thermal only problem from which much useful information can be extracted. We have applied this approach to a typical trigate device on SOI substrate. The simulated thermal resistance is in reasonable agreement with measurements. Parameters for the width dependent compact model for the thermal resistance can readily be extracted. The dependence of thermal resistance on the thickness of the bottom oxide has also been investigated. Moreover this permits transient behavior to be simulated in much more detail than is possible to be measured experimentally. Thus time constants and thermal capacitances for thermal compact models which are usually difficult to extract experimentally may be simulated numerically

Comparison of 24 GHz receiver front-ends using active and passive mixers in CMOS

This study compares the key parameters of two integrated receiver front-end architectures: low noise amplifier (LNA) with active mixer against LNA with passive mixer. The authors discuss the differences in the performance and their impact on system characteristics for radar applications. A low-IF down-conversion receiver implementation is considered. The results are compared in measurement for two 24 GHz receiver front-end chips realised in a 0.13 mum digital CMOS process. Both circuits have been characterised over automotive temperature range -40 to 125degC. The front-end with an active mixer offers lower LO power dependence and exhibits better temperature stability, whereas the front-end with a passive mixer has the advantage of better input-referred linearity and lower flicker noise.

Reduction of low-frequency noise in MOSFETs under switched gate and substrate bias

A strong reduction of MOSFET low-frequency noise under switched gate bias conditions is observed for forward substrate bias. The effect of forward substrate bias is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. This finding is explained by the physics of trap emission time constants and suggests new topologies and biasing schemes for analog CMOS circuits.

Evaluation of FinFET RF Building Blocks

In this paper we present for the first time essential building blocks for RF circuits in an advanced FinFET technology. Voltage controlled oscillators (VCOs) and a low noise amplifier (LNA) have been realized.

Advances in Multi-Gate MOSFET Circuit Design

In this paper recent advances in multi-gate MOSFET (MuGFET) circuit design are reported. The feasibility of essential parts of low-power mobile SoC applications and large scale integration capability is shown. Excellent short channel control enables undoped metal gate MuGFETs to outperfom their planar counterparts in terms of delay-leakage trade-off. Superior voltage scaling efficiency and competitive performance is demonstrated for a product typical critical path. Design and layout optimization for improved SRAM cell stability is shown. Beneficial analog performance is exemplary demonstrated for an OpAmp. A potential degradation of ADC performance due to transient Vt mismatch is shown, the use of redundancy is proposed as countermeasure. Key RF building blocks are presented, MuGFET specific design issues are outlined. A comparison of different ESD elements yields a potential ESD protection scheme combining planar and MuGFET devices.

Improved RF-performance of sub-micron CMOS transistors by asymmetrically fingered device layout

This paper presents novel MOS-transistor layouts for analog RF applications. Asymmetrical drain and source diffusion areas as well as their contacting metal stacks are adjusted to improve the transistor performance. These modifications allow for increased device currents and reduced parasitic wiring capacitances simultaneously. Ring oscillators with transistors of identical channel width and length fabricated in a 65 nm digital CMOS technology are used for verification. An increase of 14% in oscillation frequency compared to classical multi-finger layouts corroborates the improvement by these modifications.