Claudio Fiegna

Analysis of gate shot noise in MOSFETs with ultrathin gate oxides

The impact of gate shot noise associated with gate leakage current in MOSFETs is studied by means of analytical models and numerical device simulation. The effects of shot noise on the main two-port noise parameters (minimum noise figure, equivalent noise resistance, and optimum source admittance) and their dependence on oxide thickness and on the level of tunneling leakage current are analyzed.

Stability of self-consistent Monte Carlo Simulations: effects of the grid size and of the coupling scheme

In this paper, the authors show that the grid spacing affects the stability of self-consistent Monte Carlo device simulations. An analytical model is derived to describe this effect. Guidelines for the choice of the grid size are provided, showing that, when the linear Poisson scheme is used, source/drain extensions with doping level as high as 10/sup 20/ cm/sup -3/ require grid spacing lower than 1 nm in order to have stable simulations. On the other hand, the nonlinear coupling scheme does not impose any constraint, provided that the time between two solutions of the Poisson equation is so long that each solution can be considered as a stationary solution of the Boltzmann transport equation.

Physical Aspects of Cell Operation and Reliability

This chapter overviews the basic physical effects involved in programming and erasing of Flash memory cells, to provide the background for a deeper understanding of their operation and reliability. In particular, tunneling and high field transport are treated and the associated phenomena in MOS-FETs and Flash cells are described by means of measurements and simulations. Device degradation induced by charge injection into thin silicon dioxide layers is also briefly discussed.

A Monte-Carlo study of the role of scattering in deca-nanometer MOSFETs

In this paper, a Monte-Carlo simulator, including quantum corrections to the potential and an improved physically based model for surface roughness scattering is used to study the electronic transport in double gate (DG) SOI MOSFETs with L/sub G/ down to 14nm. Our results demonstrate that, for the explored L/sub G/ values, scattering still controls the ON current (I/sub DS/), which for L/sub G/ = 25nm is overestimated by about a factor of 2 by a ballistic model. By monitoring the electrons back-scattered at the source, we discuss the role of the scattering in different parts of the device.

The effects of scaling on the performance of small-signal MOS amplifiers

Abstract The impact of scaling of the CMOS technology on the performance of small-signal MOS amplifiers is evaluated by analytical models and physics-based device simulation. The limitations set by non-ideal scaling of the electrical characteristics of the MOSFET and their implications on the trade-off between power dissipation and performance are analyzed and discussed. The results reported in this paper give indications about the improvements and limitations that may be expected as the technology is scaled below 0.1 μm and provide indications regarding technology options (e.g. bulk vs. SOI MOSFETs) and different possible approaches for scaling the bias current as CMOS miniaturization proceeds.

Measurements of low field mobility in ultra-thin SOI n- and p-MOSFETs

Abstract Low-field electron and hole effective mobilities ( μ eff ) of ultra-thin SOI n- and p-MOSFETs, down to a silicon thickness T Si of approximately 5 nm, have been measured at different temperatures using a special test structure able to circumvent parasitic resistance effects. At large inversion densities ( N inv ), ultra-thin SOI exhibit higher mobility than heavily doped bulk MOS and a weak dependence of mobility on silicon thickness. However, at small N inv the mobility is clearly reduced for decreasing T Si , due to enhanced phonon scattering in the thin quantum well.

Device simulation for decananometer MOSFETs

Abstract This paper discusses the main issues related to the application of numerical device simulation to advanced decananometer-size MOSFETs. The main trends of CMOS technology evolution are analyzed and discussed with emphasis on the requirements imposed to device simulation programs suitable for application to the development of new, advanced technology generations. The main approaches for the simulation of carrier transport in silicon devices are briefly reviewed and their advantages and limitations are discussed. Finally, two examples of application of advanced physics-based device simulation to the analysis of the operation of state-of-the-art technologies are reported.

Analysis of thermal noise in scaled MOS devices and RF circuits

Abstract In this paper physics-based numerical simulation is applied to the evaluation of the noise performance of MOS devices and circuits for technologies with minimum feature size ranging from 0.25 to 0.1 μm. Adopting a simulation approach for noise calculations that considers the transistor as an active transmission line and by post-processing the results of two-dimensional hydrodynamic device simulations, a detailed analysis of the dependences of MOSFET noise parameters and minimum noise figure (NF) on bias and technology scaling is carried out. Furthermore, the impact of scaling on the performance of a simple low noise amplifier is analyzed; analytical models and physics-based device simulations provide predictions about the trend of NF and power consumption of the amplifier, for operation frequencies from 900 MHz up to 20 GHz. The results of this work confirm that noise performance improve as CMOS technology is scaled down, increasing the interest for CMOS low-noise amplifiers.

SIMULATION OF THERMAL NOISE IN SCALED MOSFETS

In this work, hydrodynamic device simulations and a post-processor for the simulation of noise in MOSFETs are applied in order to evaluate the impact of scaling on the thermal noise of transistors representative of technologies with minimum gate length scaled from 0.25 μm down to 0.1 μm. The dependences on bias and technology scaling of the spectral densities of the equivalent drain- and induced gate-noise currents are anayzed in details. The effect of technology scaling on the two-port noise parameters of the intrinsic MOSFET is studied as well. The results of this work confirm that the transistors noise performance tend to improve as the technology is scaled down, making CMOS a suitable technological option for the implementation of advanced low-power RF systems.

Analysis of strained-silicon-on-insulator double-gate MOS structures

Ultra-thin body double-gate (DG) MOS structures with strained silicon are investigated by the solution of the 1D Schrodinger and Poisson equations, with open boundary conditions on the wave functions in the gate electrodes. The electrostatics of this device architecture and its dependence on the amount of strain and on the thickness of the silicon layer is analyzed in terms of subband structure, subband population, carrier distribution within the strained-silicon layer, charge-voltage characteristics and gate tunneling current.