Domenik Helms

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

This work is a contribution to high level synthesis for lowpower systems.While device feature size decreases, interconnectpower becomes a dominating factor.Thus it is importantthat accurate physical information is used during high-level synthesis.We propose a new power optimisation algorithm for RT-levelnetlists.The optimisation performs simultaneously slicing-treestructure-based floorplanning and functional unit binding andallocation.Since floorplanning, binding and allocation can use theinformation generated by the other step, the algorithm can greatlyoptimise the interconnect power.Compared to interconnect unawarepower optimised circuits, it shows that interconnect powercan be reduced by an average of 41.2%, while reducing overallpower by 24.1% on an average.The functional unit power remainsnearly unchanged.These optimisations are not achieved atthe expense of area.

Leakage in CMOS Circuits – An Introduction

In this tutorial, we give an introduction to the increasingly important effect of leakage in recent and upcoming technologies. The sources of leakage such as subthreshold leakage, gate leakage, pn-junction leakage and further GIDL, hot-carrier effect and punchthrough are identified and analyzed separately and also under PTV variations.

Voltage- and ABB-island optimization in high level synthesis

Using our framework supporting simultaneous behavioral to RTL synthesis, component-wise floorplanning, as well as ABB (adaptive body biasing) and VDD aware power and delay prediction, we present a performance neutral methodology for optimal VDD-island generation and multiple ABB application. We show that tuning supply and body voltage for the entire design reduces the total energy dissipation by 4.6-38.1% without any performance loss. By allowing more than one body voltage and without optimizing the floorplan, the savings do not rise any further. Carefully floorplanning the design, we can additionally use VDD-islands reducing the power by 8.7-49.2%. In addition to the power savings, the power and delay variability due to PTV (process, temperature, voltage) variation can be reduced with all proposed ABB approaches, assuming that only the chip structure has to be fixed at design time, but the voltage levels can be adapted after the system manufacturing.

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

In this work we present a SPICE-based RTL subthreshold leakage model analyzing components built in 70nm technology. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude (Mukhopadhyay, 2003). We show that the leakage of RT-components still shows state dependencies between 20% and 80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed

Modelling the impact of high level leakage optimization techniques on the delay of RT-components

To adress the problem of static power consumption, approaches as ABB and AVS have been proposed to reduce runtime leakage in integrated circuits. Applying these techniques is a trade off between power and delay, which is best decided early in the design flow. Therefore high level power and delay estimation is needed. In our work, we present a fast RT Level delay macro model considering supply and bias voltages and temperature. Errors below 5% combined with only few characterization data enables this approach to be used by high level design tools to support leakage optimization by e.g. ABB and AVS.

An Improved Power Macro-Model for Arithmetic Datapath Components

We propose an improved power macro-model for arithmetic datapath components, which is based on spatio-temporal correlations of two consecutive input vectors and the output vector. Based on the enhanced Hamming-distance model [3], we introduce an additional spatial distance for the input vector and the Hamming-distance of the output vector to improve model accuracy significantly. Experimental results show that the models standard deviation is reduced by 3% for small components and up to 23% for complex components. Because of its fast and accurate power prediction, this model can be used for fast high-level power analysis.

RTL power modeling and estimation of sleep transistor based power gating

We present an accurate RT level estimation methodology describing the power consumption of a component under power gating. By developing separate models for the on- and off-state and the transition cost between them, we can limit errors to below 10% compared to SPICE. The models support several implementation styles of power gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate. We show, how the models can be integrated into a high level power estimation framework supporting design space exploration for several design for leakage methodologies.

Efficient NBTI modeling technique considering recovery effects

The aging effect “Negative Bias Temperature Instability”, which is highly dependent on device history, has a direct impact on the design of integrated circuits. In order to make realistic predictions available in the design process, simulation durations of existing history aware models must be significantly reduced. Therefore, a performance-oriented, yet accurate abstraction of the switching trap NBTI model is presented within this paper. Evaluation results for various stress scenarios demonstrate very precise NBTI simulations and a major improvement to another performance-oriented model abstraction. Simulation durations facilitate realistic aging predictions of larger components in a reasonable period of time.

Behavioral-level thermal- and aging-estimation flow

In recent transistor technologies design metrics highly interdepend on each other and cannot be regarded isolated. For example temperature analysis requires detailed knowledge of the power consumption and leakage currents exponentially depend on the temperature. Additionally long-term aging- or degradation-effects such as electromigration and NBTI occur in recent designs and need to be considered too. For these reasons we propose a flow applying run-time efficient and accurate methods and tools from the power-, thermal-, and aging-estimation domain in combination with a model describing the physical properties of the IC package design. The flow iterates the parameter estimation to handle all interdependencies and results in a steady state after few runs and only seconds of execution time.

Accurate PTV, state, and ABB aware RTL blackbox modeling of subthreshold, gate, and PN-Junction leakage

We present a blackbox approach to model leakage currents of RTL data-path components. The model inputs are temperature, VDD, body voltage of NMOS and PMOS and the bitvector at the input. Additionally, the model accepts a statistical Gaussian variation introduced by intra-die and systematic variation introduced by inter-die. Both variations can be given independently for each BSIM-level process parameter; in this work we evaluate variation of channel length, gate-oxide thickness and channel doping. Model output is the sum of subthreshold, gate, and pn-junction leakage. The evaluation of an RT component can be done in milliseconds and the result for the 45nm and 65nm BPTM technology is within 2% against single BSIM4.40 evaluation and within 5% against statistical BSIM4.40 evaluation assuming 1% variation of the process parameters.