Sven Rosinger

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.

RTL power modeling and estimation of sleep transistor based power gating

We present an accurate RT level estimation methodology describing the power consumption of a component under power gating. By developing separate models for the on- and off-state and the transition cost between them, we can limit errors to below 10% compared to SPICE. The models support several implementation styles of power gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate. We show, how the models can be integrated into a high level power estimation framework supporting design space exploration for several design for leakage methodologies.

COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration

The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties that enables fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow is currently under implementation in the COMPLEX FP7 European integrated project.

Behavioral-level thermal- and aging-estimation flow

In recent transistor technologies design metrics highly interdepend on each other and cannot be regarded isolated. For example temperature analysis requires detailed knowledge of the power consumption and leakage currents exponentially depend on the temperature. Additionally long-term aging- or degradation-effects such as electromigration and NBTI occur in recent designs and need to be considered too. For these reasons we propose a flow applying run-time efficient and accurate methods and tools from the power-, thermal-, and aging-estimation domain in combination with a model describing the physical properties of the IC package design. The flow iterates the parameter estimation to handle all interdependencies and results in a steady state after few runs and only seconds of execution time.

The M2DC Project: Modular Microserver DataCentre

The Modular Microserver DataCentre (M2DC) project will investigate, develop and demonstrate a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous microserver computing resources, being able to be tailored to meet requirements from various application domains such as image processing, cloud computing or HPC. M2DC will be built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated, advanced management strategies and system efficiency enhancements (SEE), well-defined interfaces to surrounding software data centre ecosystem.

Autonomous Flight Control Meets Custom Payload Processing: A Mixed-Critical Avionics Architecture Approach for Civilian UAVs

Multi-rotor Unmanned Aerial Vehicles (UAVs) are interesting for commercial as well as for private use. Simple tasks like aerial photography are well known, but nowadays new scenarios, like on-board video processing or complex sensor data processing, are gaining in importance. These scenarios require high-performance on-board processing which is not available in most of todays avionics architectures for civilian multi-rotor systems. Due to the limited installation space and weight requirements, the usage of highly integrated Multi-Processor System on Chips (MPSoCs), capable to implement real-time critical flight control algorithms and compute intensive custom payload functions is appealing. This paper presents fundamental requirements on the architecture and flight control algorithms of existing autonomously flying commercial multi-rotor UAVs. On this basis a new approach for an avionics architecture using the Xilinx ZYNQ (MPSoC) is proposed. In combination with the presentation of the proposed architecture new challenges will be discussed that result from the integration of mixed-critical applications on a single chip.

Data centres for IoT applications: The M2DC approach (Invited paper)

The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to surrounding software data centre ecosystem.

Power Management Aware Low Leakage Behavioural Synthesis

Different power management techniques have been developed to target leakage-reduction at runtime of a design by orders of magnitude. To advance an optimization, different power modes and especially costs of state transitions have to be considered in early steps, e.g. during scheduling, allocation and binding of high-level synthesis. We present an operation scheduling, binding and allocation approach that includes different power modes into optimization to support an efficient power management. Our ILP-based scheduling performs an operation clustering and serves as a heuristic to minimize the amount of power state transitions. In the subsequent binding, operations are then bound to resources cluster-wise, which can be put to sleep states for longer continuous times. The evaluation shows that the high gain of power management (in our work power gating) is increased by up to further 31.1% compared to a high level synthesis approach that neglects power management during optimization. These leakage savings only base on synthesis improvements and do not introduce extra costs in terms of area or delay.

M2DC – Modular Microserver DataCentre with heterogeneous hardware

The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous microserver computing resources. The resulting server architecture will be able to be tailored to meet requirements from a wide range of application domains. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to the surrounding software data centre ecosystem. In this paper, we focus in particular on the thermal management strategies and on the initial benchmarking of the Aarch64 ARM architecture.

Phase Space Based NBTI Model

A phase space based NBTI model that relies upon the well-known reaction-diffusion model is introduced. Temporal shift in threshold voltage and a new parameter called “healability” are used to characterize the state of the NBTI effect. The NBTI degradation is then simulated as a trace of the interpolated characterization parameters. Thereby, healability is crucial for the success of the model. The phase space based model is well suitable in performance oriented use cases, since a small deterioration of the simulation results comes with a vastly improved simulation speed. The additional phase space dimensions of temperature and supply voltage in combination with the conversion between duty cycle and supply voltage permit a performance efficient way to simulate NBTI degradation for complete circuits without disregarding power gating, temperature profiles and the IR drop.