Donald D. Shugard

Experiments using automatic physical design techniques for optimizing circuit performance

A system that accepts a transistor level net list, tunes it for high performance, and automatically lays it out is described. The system consists primarily of two components, TILOS and SC2D. The first component, TILOS, adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures are described, and their effect is illustrated with several examples, ranging from a few dozens of transistors to tens of thousands.<<ETX>>

Placement algorithms for CMOS cell synthesis

Heuristic placement algorithms for the layout synthesis of CMOS logic cells are described. The techniques are not restricted to fully complimentary CMOS, and focus on a novel strategy for FET pair ordering which takes advantage of splitting wide FETs to eliminate diffusion gaps. These algorithms are applicable to strip-based layout synthesis from transistor netlists. Existing CMOS cell synthesis systems neither fully include the costs nor utilize the benefits of FET splitting. The system described does this, in some cases results in an area saving. In general, it trades diffusion gaps for useful FETs. Since some technologies penalize diffusion gaps heavily, and others, such as sea-of-gates, forbid them altogether, such a tradeoff seems increasingly appropriate.<<ETX>>

A set of switch-level synthesis tools

A set of switch-level synthesis tools is described. First, a tool, called sea-of-devices (SOD), that accepts an arbitrary transistor-level schematic and produces a gate-matrix style layout on a virtual grid is presented. The output is run through a compactor that does technology binding (MACS). Because it is a true cell compiler, SOD does not make use of any library of predefined cells: each subcircuit is laid out from scratch each time the tool is run. This means that the system can accept any circuit, including ones with individually sized transistors, such as those produced by the TILOS transistor sizer. Typical runs of SOD are in the 50-5000 transistor range. A tool which provides an efficient way to specify transistor circuits not limited to libraries, called the Switch-Level IC Compiler (SLICC), is discussed. It translates a subset of C directly into transistors, again without using any library, SLIC understands local logic transformations and CMOS rules (e.g. complementary and pass logic). It is not a general logic optimizer, but can accept the output of such a tool. The pipeline of a design is followed through SLICC, TILOS, SOD, and MACS.<<ETX>>